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https://github.com/c64scene-ar/llvm-6502.git
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ARM scheduler model: Add scheduler info to more instructions and resource
descriptions for compares git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer
parent
3341538be6
commit
fc61e635fd
@ -1214,7 +1214,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
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PatFrag opnode, bit Commutable = 0> {
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def ri : AI1<opcod, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, iii,
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opc, "\t$Rn, $imm",
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[(opnode GPR:$Rn, so_imm:$imm)]> {
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[(opnode GPR:$Rn, so_imm:$imm)]>,
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Sched<[WriteCMP, ReadALU]> {
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bits<4> Rn;
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bits<12> imm;
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let Inst{25} = 1;
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@ -1227,7 +1228,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
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}
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def rr : AI1<opcod, (outs), (ins GPR:$Rn, GPR:$Rm), DPFrm, iir,
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opc, "\t$Rn, $Rm",
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[(opnode GPR:$Rn, GPR:$Rm)]> {
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[(opnode GPR:$Rn, GPR:$Rm)]>,
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Sched<[WriteCMP, ReadALU, ReadALU]> {
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bits<4> Rn;
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bits<4> Rm;
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let isCommutable = Commutable;
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@ -1243,7 +1245,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
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def rsi : AI1<opcod, (outs),
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(ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm, iis,
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opc, "\t$Rn, $shift",
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[(opnode GPR:$Rn, so_reg_imm:$shift)]> {
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[(opnode GPR:$Rn, so_reg_imm:$shift)]>,
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Sched<[WriteCMPsi, ReadALU]> {
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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@ -1259,7 +1262,8 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc,
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def rsr : AI1<opcod, (outs),
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(ins GPRnopc:$Rn, so_reg_reg:$shift), DPSoRegRegFrm, iis,
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opc, "\t$Rn, $shift",
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[(opnode GPRnopc:$Rn, so_reg_reg:$shift)]> {
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[(opnode GPRnopc:$Rn, so_reg_reg:$shift)]>,
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Sched<[WriteCMPsr, ReadALU]> {
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bits<4> Rn;
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bits<12> shift;
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let Inst{25} = 0;
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@ -1341,7 +1345,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
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[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALU, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> imm;
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@ -1353,7 +1358,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
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[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALU, ReadALU, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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@ -1368,7 +1374,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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(ins GPR:$Rn, so_reg_imm:$shift),
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DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
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[(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALUsi, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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@ -1384,7 +1391,8 @@ multiclass AI1_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode,
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DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
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[(set GPRnopc:$Rd, CPSR,
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(opnode GPRnopc:$Rn, so_reg_reg:$shift, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALUsr, ReadALUsr]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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@ -1407,7 +1415,8 @@ multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
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DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
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[(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALU, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> imm;
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@ -1418,7 +1427,8 @@ multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
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}
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def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
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DPFrm, IIC_iALUr, opc, "\t$Rd, $Rn, $Rm",
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[/* pattern left blank */]> {
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[/* pattern left blank */]>,
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Sched<[WriteALU, ReadALU, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<4> Rm;
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@ -1431,7 +1441,8 @@ multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def rsi : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_imm:$shift),
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DPSoRegImmFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
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[(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALUsi, ReadALU]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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@ -1445,7 +1456,8 @@ multiclass AI1_rsc_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def rsr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg_reg:$shift),
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DPSoRegRegFrm, IIC_iALUsr, opc, "\t$Rd, $Rn, $shift",
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[(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn, CPSR))]>,
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Requires<[IsARM]> {
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Requires<[IsARM]>,
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Sched<[WriteALUsr, ReadALUsr]> {
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bits<4> Rd;
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bits<4> Rn;
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bits<12> shift;
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@ -1857,7 +1869,8 @@ let neverHasSideEffects = 1, isReMaterializable = 1 in
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// the instruction. The {24-21} opcode bits are set by the fixup, as we don't
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// know until then which form of the instruction will be used.
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def ADR : AI1<{0,?,?,0}, (outs GPR:$Rd), (ins adrlabel:$label),
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MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []> {
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MiscFrm, IIC_iALUi, "adr", "\t$Rd, $label", []>,
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Sched<[WriteALU, ReadALU]> {
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bits<4> Rd;
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bits<14> label;
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let Inst{27-25} = 0b001;
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@ -3881,28 +3894,33 @@ def UDIV : ADivA1I<0b011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), IIC_iDIV,
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def CLZ : AMiscA1I<0b000010110, 0b0001, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "clz", "\t$Rd, $Rm",
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[(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>;
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[(set GPR:$Rd, (ctlz GPR:$Rm))]>, Requires<[IsARM, HasV5T]>,
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Sched<[WriteALU]>;
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def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "rbit", "\t$Rd, $Rm",
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[(set GPR:$Rd, (ARMrbit GPR:$Rm))]>,
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Requires<[IsARM, HasV6T2]>;
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Requires<[IsARM, HasV6T2]>,
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Sched<[WriteALU]>;
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def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "rev", "\t$Rd, $Rm",
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[(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
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[(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>,
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Sched<[WriteALU]>;
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let AddedComplexity = 5 in
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def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "rev16", "\t$Rd, $Rm",
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[(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
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Requires<[IsARM, HasV6]>;
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Requires<[IsARM, HasV6]>,
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Sched<[WriteALU]>;
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let AddedComplexity = 5 in
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def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
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IIC_iUNAr, "revsh", "\t$Rd, $Rm",
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[(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
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Requires<[IsARM, HasV6]>;
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Requires<[IsARM, HasV6]>,
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Sched<[WriteALU]>;
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def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
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(and (srl GPR:$Rm, (i32 8)), 0xFF)),
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@ -3914,7 +3932,8 @@ def PKHBT : APKHI<0b01101000, 0, (outs GPRnopc:$Rd),
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[(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF),
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(and (shl GPRnopc:$Rm, pkh_lsl_amt:$sh),
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0xFFFF0000)))]>,
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Requires<[IsARM, HasV6]>;
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Requires<[IsARM, HasV6]>,
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Sched<[WriteALUsi, ReadALU]>;
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// Alternate cases for PKHBT where identities eliminate some nodes.
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def : ARMV6Pat<(or (and GPRnopc:$Rn, 0xFFFF), (and GPRnopc:$Rm, 0xFFFF0000)),
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@ -3930,7 +3949,8 @@ def PKHTB : APKHI<0b01101000, 1, (outs GPRnopc:$Rd),
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[(set GPRnopc:$Rd, (or (and GPRnopc:$Rn, 0xFFFF0000),
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(and (sra GPRnopc:$Rm, pkh_asr_amt:$sh),
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0xFFFF)))]>,
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Requires<[IsARM, HasV6]>;
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Requires<[IsARM, HasV6]>,
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Sched<[WriteALUsi, ReadALU]>;
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// Alternate cases for PKHTB where identities eliminate some nodes. Note that
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// a shift amount of 0 is *not legal* here, it is PKHBT instead.
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@ -64,6 +64,11 @@ def WriteALUsr : SchedWrite; // Shift by register.
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def WriteALUSsr : SchedWrite; // Shift by register (flag setting).
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def ReadALUsr : SchedRead; // Some operands are read later.
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// Compares.
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def WriteCMP : SchedWrite;
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def WriteCMPsi : SchedWrite;
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def WriteCMPsr : SchedWrite;
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// Define TII for use in SchedVariant Predicates.
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def : PredicateProlog<[{
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const ARMBaseInstrInfo *TII =
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@ -1920,7 +1920,7 @@ def A9WriteI : SchedWriteRes<[A9UnitALU]>;
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def A9WriteIsr : SchedWriteRes<[A9UnitALU]> { let Latency = 2; }
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// Basic ALU.
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def : WriteRes<WriteALU, [A9UnitALU]>;
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def A9WriteALU : SchedWriteRes<[A9UnitALU]>;
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// ALU with operand shifted by immediate.
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def : WriteRes<WriteALUsi, [A9UnitALU]> { let Latency = 2; }
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// ALU with operand shifted by register.
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@ -2278,7 +2278,7 @@ def A9Read4 : SchedReadAdvance<3>;
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def :ItinRW<[A9WriteI], [IIC_iMOVi,IIC_iMOVr,IIC_iMOVsi,
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IIC_iMVNi,IIC_iMVNsi,
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IIC_iCMOVi,IIC_iCMOVr,IIC_iCMOVsi]>;
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def :ItinRW<[A9WriteI,ReadALU],[IIC_iMVNr]>;
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def :ItinRW<[A9WriteI,A9ReadALU],[IIC_iMVNr]>;
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def :ItinRW<[A9WriteIsr], [IIC_iMOVsr,IIC_iMVNsr,IIC_iCMOVsr]>;
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def :ItinRW<[A9WriteI2], [IIC_iMOVix2,IIC_iCMOVix2]>;
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@ -2286,13 +2286,13 @@ def :ItinRW<[A9WriteI2pc], [IIC_iMOVix2addpc]>;
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def :ItinRW<[A9WriteI2ld], [IIC_iMOVix2ld]>;
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def :ItinRW<[WriteALU], [IIC_iBITi,IIC_iBITr,IIC_iUNAr,IIC_iTSTi,IIC_iTSTr]>;
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def :ItinRW<[WriteALU, ReadALU], [IIC_iALUi, IIC_iCMPi, IIC_iCMPsi]>;
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def :ItinRW<[WriteALU, ReadALU, ReadALU],[IIC_iALUr,IIC_iCMPr]>;
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def :ItinRW<[WriteALU, A9ReadALU], [IIC_iALUi, IIC_iCMPi, IIC_iCMPsi]>;
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def :ItinRW<[WriteALU, A9ReadALU, A9ReadALU],[IIC_iALUr,IIC_iCMPr]>;
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def :ItinRW<[WriteALUsi], [IIC_iBITsi,IIC_iUNAsi,IIC_iEXTr,IIC_iTSTsi]>;
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def :ItinRW<[WriteALUsi, ReadALU], [IIC_iALUsi]>;
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def :ItinRW<[WriteALUsi, ReadDefault, ReadALU], [IIC_iALUsir]>; // RSB
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def :ItinRW<[WriteALUsi, A9ReadALU], [IIC_iALUsi]>;
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def :ItinRW<[WriteALUsi, ReadDefault, A9ReadALU], [IIC_iALUsir]>; // RSB
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def :ItinRW<[A9WriteALUsr], [IIC_iBITsr,IIC_iTSTsr,IIC_iEXTAr,IIC_iEXTAsr]>;
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def :ItinRW<[A9WriteALUsr, ReadALU], [IIC_iALUsr,IIC_iCMPsr]>;
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def :ItinRW<[A9WriteALUsr, A9ReadALU], [IIC_iALUsr,IIC_iCMPsr]>;
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// A9WriteHi ignored for MUL32.
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def :ItinRW<[A9WriteM, A9WriteMHi], [IIC_iMUL32,IIC_iMAC32,
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@ -2482,9 +2482,15 @@ def :ItinRW<[A9WriteV9, A9Read2, A9Read2], [IIC_VRECSD]>;
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def :ItinRW<[A9WriteV10, A9Read2, A9Read2], [IIC_VRECSQ]>;
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// Map SchedRWs that are identical for cortexa9 to existing resources.
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def : SchedAlias<WriteALU, A9WriteALU>;
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def : SchedAlias<WriteALUsr, A9WriteALUsr>;
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def : SchedAlias<WriteALUSsr, A9WriteALUsr>;
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def : SchedAlias<ReadALU, A9ReadALU>;
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def : SchedAlias<ReadALUsr, A9ReadALU>;
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// FIXME: need to special case AND, ORR, EOR, BIC because they don't read
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// advance. But our instrinfo claims it does.
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def : SchedAlias<WriteCMP, A9WriteALU>;
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def : SchedAlias<WriteCMPsi, A9WriteALU>;
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def : SchedAlias<WriteCMPsr, A9WriteALU>;
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} // SchedModel = CortexA9Model
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@ -1113,23 +1113,22 @@ let SchedModel = SwiftModel in {
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def SwiftWriteALUsi : SchedWriteVariant<[
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// lsl #2, lsl #1, or lsr #1.
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SchedVar<IsFastImmShiftSwiftPred, [SwiftWriteP01TwoCycle]>,
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// Arbitrary imm shift.
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SchedVar<NoSchedPred, [WriteALU]>
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]>;
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def SwiftWriteALUsr : SchedWriteVariant<[
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SchedVar<IsPredicatedPred, [SwiftWriteP01ThreeCycleTwoUops]>,
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SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
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SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
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]>;
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def SwiftWriteALUSsr : SchedWriteVariant<[
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SchedVar<IsPredicatedPred, [SwiftWriteP0ThreeCycleThreeUops]>,
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SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
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SchedVar<NoSchedPred, [SwiftWriteP01TwoCycle]>
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]>;
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def SwiftReadAdvanceALUsr : SchedReadVariant<[
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SchedVar<IsPredicatedPred, [SchedReadAdvance<2>]>,
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SchedVar<NoSchedPred, [NoReadAdvance]>
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SchedVar<NoSchedPred, [NoReadAdvance]>
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]>;
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// ADC,ADD,NEG,RSB,RSC,SBC,SUB,ADR
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// AND,BIC, EOR,ORN,ORR
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// AND,BIC,EOR,ORN,ORR
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// CLZ,RBIT,REV,REV16,REVSH,PKH
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def : WriteRes<WriteALU, [SwiftUnitP01]>;
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def : SchedAlias<WriteALUsi, SwiftWriteALUsi>;
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@ -1137,4 +1136,9 @@ let SchedModel = SwiftModel in {
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def : SchedAlias<WriteALUSsr, SwiftWriteALUSsr>;
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def : ReadAdvance<ReadALU, 0>;
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def : SchedAlias<ReadALUsr, SwiftReadAdvanceALUsr>;
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// 4.2.5 Integer comparison
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def : WriteRes<WriteCMP, [SwiftUnitP01]>;
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def : WriteRes<WriteCMPsi, [SwiftUnitP01]>;
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def : WriteRes<WriteCMPsr, [SwiftUnitP01]>;
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}
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