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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman 2008-11-21 19:16:58 +00:00
parent 3ebd0eeaeb
commit fc626b62b8
1 changed files with 9 additions and 9 deletions
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18
lib/CodeGen/ScheduleDAGInstrs.cpp
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@ -50,14 +50,14 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!");
std::vector<SUnit *> &UseList = Uses[Reg]; std::vector<SUnit *> &UseList = Uses[Reg];
SUnit *&Def = Defs[Reg]; SUnit *&Def = Defs[Reg];
// Optionally add output and anti dependences. // Optionally add output and anti dependencies.
if (Def && Def != SU) if (Def && Def != SU)
Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false, Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
/*PhyReg=*/Reg, Cost, /*isAntiDep=*/MO.isUse()); /*PhyReg=*/Reg, Cost, /*isAntiDep=*/MO.isUse());
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
SUnit *&Def = Defs[*Alias]; SUnit *&Def = Defs[*Alias];
if (Def && Def != SU) if (Def && Def != SU)
Def->addPred(SU, /*isCtrl=*/true, /*isSpecial=*/false, Def->addPred(SU, /*isCtrl=*/true, /*isArtificial=*/false,
/*PhyReg=*/*Alias, Cost); /*PhyReg=*/*Alias, Cost);
} }
@ -65,13 +65,13 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
// Add any data dependencies. // Add any data dependencies.
for (unsigned i = 0, e = UseList.size(); i != e; ++i) for (unsigned i = 0, e = UseList.size(); i != e; ++i)
if (UseList[i] != SU) if (UseList[i] != SU)
UseList[i]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false, UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
/*PhysReg=*/Reg, Cost); /*PhysReg=*/Reg, Cost);
for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
std::vector<SUnit *> &UseList = Uses[*Alias]; std::vector<SUnit *> &UseList = Uses[*Alias];
for (unsigned i = 0, e = UseList.size(); i != e; ++i) for (unsigned i = 0, e = UseList.size(); i != e; ++i)
if (UseList[i] != SU) if (UseList[i] != SU)
UseList[i]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false, UseList[i]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false,
/*PhysReg=*/*Alias, Cost); /*PhysReg=*/*Alias, Cost);
} }
@ -85,18 +85,18 @@ void ScheduleDAGInstrs::BuildSchedUnits() {
bool True = true; bool True = true;
if (!MI->isSafeToMove(TII, False)) { if (!MI->isSafeToMove(TII, False)) {
if (Chain) if (Chain)
Chain->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false); Chain->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k) for (unsigned k = 0, m = PendingLoads.size(); k != m; ++k)
PendingLoads[k]->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false); PendingLoads[k]->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
PendingLoads.clear(); PendingLoads.clear();
Chain = SU; Chain = SU;
} else if (!MI->isSafeToMove(TII, True)) { } else if (!MI->isSafeToMove(TII, True)) {
if (Chain) if (Chain)
Chain->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false); Chain->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
PendingLoads.push_back(SU); PendingLoads.push_back(SU);
} }
if (Terminator && SU->Succs.empty()) if (Terminator && SU->Succs.empty())
Terminator->addPred(SU, /*isCtrl=*/false, /*isSpecial=*/false); Terminator->addPred(SU, /*isCtrl=*/false, /*isArtificial=*/false);
if (MI->getDesc().isTerminator() || MI->isLabel()) if (MI->getDesc().isTerminator() || MI->isLabel())
Terminator = SU; Terminator = SU;