mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 05:32:25 +00:00
Convert all I<> instructions to asmformat.
Delete the 'name' field of all instructions that have asmformats. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15403 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
4ae131e5da
commit
fc752713d7
@ -126,7 +126,7 @@ class DF { bits<4> Prefix = 10; }
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//===----------------------------------------------------------------------===//
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// Instruction templates...
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class I<string n, bits<8> o, Format f> : X86Inst<n, o, f, NoMem, NoImm>;
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class I<bits<8> o, Format f> : X86Inst<"", o, f, NoMem, NoImm>;
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class Im<string n, bits<8> o, Format f, MemType m> : X86Inst<n, o, f, m, NoImm>;
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class Im8 <string n, bits<8> o, Format f> : Im<n, o, f, Mem8 >;
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@ -149,17 +149,16 @@ class Im32i8<string n, bits<8> o, Format f> : X86Inst<n, o, f, Mem32, Imm8>;
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// Instruction list...
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//
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def PHI : I<"PHI", 0, Pseudo>; // PHI node...
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def NOOP : I<"nop", 0x90, RawFrm>, // nop
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II<(ops), "nop">;
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def PHI : I<0, Pseudo>; // PHI node.
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def NOOP : I<0x90, RawFrm>, II<(ops), "nop">; // nop
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def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>;
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def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>;
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def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>;
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def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>;
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def ADJCALLSTACKDOWN : I<0, Pseudo>;
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def ADJCALLSTACKUP : I<0, Pseudo>;
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def IMPLICIT_USE : I<0, Pseudo>;
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def IMPLICIT_DEF : I<0, Pseudo>;
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let isTerminator = 1 in
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let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in
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def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>;
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def FP_REG_KILL : I<0, Pseudo>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions...
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@ -167,27 +166,26 @@ let isTerminator = 1 in
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// Return instruction...
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let isTerminator = 1, isReturn = 1, isBarrier = 1 in
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def RET : I<"ret", 0xC3, RawFrm>,
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II<(ops), "ret">;
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def RET : I<0xC3, RawFrm>, II<(ops), "ret">;
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// All branches are RawFrm, Void, Branch, and Terminators
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let isBranch = 1, isTerminator = 1 in
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class IBr<string name, bits<8> opcode> : I<name, opcode, RawFrm>;
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class IBr<bits<8> opcode> : I<opcode, RawFrm>;
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let isBarrier = 1 in
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def JMP : IBr<"jmp", 0xE9>;
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def JB : IBr<"jb" , 0x82>, TB;
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def JAE : IBr<"jae", 0x83>, TB;
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def JE : IBr<"je" , 0x84>, TB;
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def JNE : IBr<"jne", 0x85>, TB;
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def JBE : IBr<"jbe", 0x86>, TB;
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def JA : IBr<"ja" , 0x87>, TB;
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def JS : IBr<"js" , 0x88>, TB;
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def JNS : IBr<"jns", 0x89>, TB;
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def JL : IBr<"jl" , 0x8C>, TB;
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def JGE : IBr<"jge", 0x8D>, TB;
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def JLE : IBr<"jle", 0x8E>, TB;
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def JG : IBr<"jg" , 0x8F>, TB;
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def JMP : IBr<0xE9>, II<(ops i32imm:$dst), "jmp $dst">;
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def JB : IBr<0x82>, TB, II<(ops i32imm:$dst), "jb $dst">;
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def JAE : IBr<0x83>, TB, II<(ops i32imm:$dst), "jae $dst">;
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def JE : IBr<0x84>, TB, II<(ops i32imm:$dst), "je $dst">;
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def JNE : IBr<0x85>, TB, II<(ops i32imm:$dst), "jne $dst">;
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def JBE : IBr<0x86>, TB, II<(ops i32imm:$dst), "jbe $dst">;
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def JA : IBr<0x87>, TB, II<(ops i32imm:$dst), "ja $dst">;
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def JS : IBr<0x88>, TB, II<(ops i32imm:$dst), "js $dst">;
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def JNS : IBr<0x89>, TB, II<(ops i32imm:$dst), "jns $dst">;
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def JL : IBr<0x8C>, TB, II<(ops i32imm:$dst), "jl $dst">;
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def JGE : IBr<0x8D>, TB, II<(ops i32imm:$dst), "jge $dst">;
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def JLE : IBr<0x8E>, TB, II<(ops i32imm:$dst), "jle $dst">;
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def JG : IBr<0x8F>, TB, II<(ops i32imm:$dst), "jg $dst">;
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//===----------------------------------------------------------------------===//
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@ -196,8 +194,8 @@ def JG : IBr<"jg" , 0x8F>, TB;
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let isCall = 1 in
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// All calls clobber the non-callee saved registers...
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let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in {
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def CALLpcrel32 : I <"call", 0xE8, RawFrm>;
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def CALL32r : I <"call", 0xFF, MRM2r>;
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def CALLpcrel32 : X86Inst<"call", 0xE8, RawFrm, NoMem, NoImm>; // FIXME: 'call' doesn't allow 'OFFSET'
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def CALL32r : I<0xFF, MRM2r>, II<(ops R32:$dst), "call $dst">;
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def CALL32m : Im32<"call", 0xFF, MRM2m>;
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}
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@ -205,16 +203,22 @@ let isCall = 1 in
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions...
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//
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def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>,
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def LEAVE : I<0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>,
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II<(ops), "leave">;
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def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>;
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def POP32r : I<0x58, AddRegFrm>, Imp<[ESP],[ESP]>,
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II<(ops R32:$reg), "pop $reg">;
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let isTwoAddress = 1 in // R32 = bswap R32
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def BSWAP32r : I<"bswap", 0xC8, AddRegFrm>, TB;
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def BSWAP32r : I<0xC8, AddRegFrm>, TB,
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II<(ops R32:$dst, R32:$src), "bswap $dst">;
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def XCHG8rr : I<0x86, MRMDestReg>, // xchg R8, R8
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II<(ops R8:$src1, R8:$src2), "xchg $src1, $src2">;
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def XCHG16rr : I<0x87, MRMDestReg>, OpSize, // xchg R16, R16
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II<(ops R16:$src1, R16:$src2), "xchg $src1, $src2">;
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def XCHG32rr : I<0x87, MRMDestReg>, // xchg R32, R32
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II<(ops R32:$src1, R32:$src2), "xchg $src1, $src2">;
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def XCHG8rr : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8
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def XCHG16rr : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16
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def XCHG32rr : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32
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def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8
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def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16
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def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32
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@ -226,72 +230,66 @@ def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem]
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def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem]
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def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP,
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def REP_MOVSB : I<0xA4, RawFrm>, REP,
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
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II<(ops), "rep movsb">;
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def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize,
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def REP_MOVSW : I<0xA5, RawFrm>, REP, OpSize,
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
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II<(ops), "rep movsw">;
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def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP,
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def REP_MOVSD : I<0xA5, RawFrm>, REP,
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Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>,
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II<(ops), "rep movsd">;
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def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP,
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def REP_STOSB : I<0xAA, RawFrm>, REP,
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Imp<[AL,ECX,EDI], [ECX,EDI]>,
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II<(ops), "rep stosb">;
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def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize,
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def REP_STOSW : I<0xAB, RawFrm>, REP, OpSize,
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Imp<[AX,ECX,EDI], [ECX,EDI]>,
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II<(ops), "rep stosw">;
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def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP,
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def REP_STOSD : I<0xAB, RawFrm>, REP,
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Imp<[EAX,ECX,EDI], [ECX,EDI]>,
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II<(ops), "rep stosd">;
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//===----------------------------------------------------------------------===//
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// Input/Output Instructions...
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//
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def IN8rr : I<"in", 0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX
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def IN8rr : I<0xEC, RawFrm>, Imp<[DX], [AL]>, // AL = in I/O address DX
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II<(ops), "in %AL, %DX">;
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def IN16rr : I<"in", 0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX
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def IN16rr : I<0xED, RawFrm>, Imp<[DX], [AX]>, OpSize, // AX = in I/O address DX
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II<(ops), "in %AX, %DX">;
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def IN32rr : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX
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def IN32rr : I<0xED, RawFrm>, Imp<[DX],[EAX]>, // EAX = in I/O address DX
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II<(ops), "in %EAX, %DX">;
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def IN8ri : Ii16<"in", 0xE4, RawFrm>, Imp<[], [AL]>, // AL = in [I/O address]
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def IN8ri : Ii16<"", 0xE4, RawFrm>, Imp<[], [AL]>, // AL = in [I/O address]
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II<(ops i16imm:$port), "in %AL, $port">;
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def IN16ri : Ii16<"in", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize, // AX = in [I/O address]
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def IN16ri : Ii16<"", 0xE5, RawFrm>, Imp<[], [AX]>, OpSize, // AX = in [I/O address]
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II<(ops i16imm:$port), "in %AX, $port">;
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def IN32ri : Ii16<"in", 0xE5, RawFrm>, Imp<[],[EAX]>, // EAX = in [I/O address]
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def IN32ri : Ii16<"", 0xE5, RawFrm>, Imp<[],[EAX]>, // EAX = in [I/O address]
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II<(ops i16imm:$port), "in %EAX, $port">;
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def OUT8rr : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>,
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def OUT8rr : I<0xEE, RawFrm>, Imp<[DX, AL], []>,
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II<(ops), "out %DX, %AL">;
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def OUT16rr : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize,
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def OUT16rr : I<0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize,
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II<(ops), "out %DX, %AX">;
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def OUT32rr : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>,
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def OUT32rr : I<0xEF, RawFrm>, Imp<[DX, EAX], []>,
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II<(ops), "out %DX, %EAX">;
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def OUT8ir : Ii16<"out", 0xE6, RawFrm>, Imp<[AL], []>,
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def OUT8ir : Ii16<"", 0xE6, RawFrm>, Imp<[AL], []>,
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II<(ops i16imm:$port), "out $port, %AL">;
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def OUT16ir : Ii16<"out", 0xE7, RawFrm>, Imp<[AX], []>, OpSize,
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def OUT16ir : Ii16<"", 0xE7, RawFrm>, Imp<[AX], []>, OpSize,
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II<(ops i16imm:$port), "out $port, %AX">;
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def OUT32ir : Ii16<"out", 0xE7, RawFrm>, Imp<[EAX], []>,
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def OUT32ir : Ii16<"", 0xE7, RawFrm>, Imp<[EAX], []>,
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II<(ops i16imm:$port), "out $port, %EAX">;
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//===----------------------------------------------------------------------===//
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// Move Instructions...
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//
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def MOV8rr : I <"mov", 0x88, MRMDestReg>,
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II<(ops R8:$dst, R8:$src), "mov $dst, $src">;
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def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize,
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II<(ops R16:$dst, R16:$src), "mov $dst, $src">;
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def MOV32rr : I <"mov", 0x89, MRMDestReg>,
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II<(ops R32:$dst, R32:$src), "mov $dst, $src">;
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def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >,
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II<(ops R8:$dst, i8imm:$src), "mov $dst, $src">;
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def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize,
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II<(ops R16:$dst, i16imm:$src), "mov $dst, $src">;
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def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >,
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II<(ops R32:$dst, i32imm:$src), "mov $dst, $src">;
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def MOV8rr : I<0x88, MRMDestReg>, II<(ops R8 :$dst, R8 :$src), "mov $dst, $src">;
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def MOV16rr : I<0x89, MRMDestReg>, OpSize, II<(ops R16:$dst, R16 :$src), "mov $dst, $src">;
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def MOV32rr : I<0x89, MRMDestReg>, II<(ops R32:$dst, R32 :$src), "mov $dst, $src">;
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def MOV8ri : Ii8 <"", 0xB0, AddRegFrm >, II<(ops R8 :$dst, i8imm :$src), "mov $dst, $src">;
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def MOV16ri : Ii16 <"", 0xB8, AddRegFrm >, OpSize, II<(ops R16:$dst, i16imm:$src), "mov $dst, $src">;
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def MOV32ri : Ii32 <"", 0xB8, AddRegFrm >, II<(ops R32:$dst, i32imm:$src), "mov $dst, $src">;
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def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8
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def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16
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def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32
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@ -309,36 +307,43 @@ def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32
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//
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// Extra precision multiplication
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def MUL8r : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8
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def MUL16r : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16
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def MUL32r : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32
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def MUL8r : I<0xF6, MRM4r>, Imp<[AL],[AX]>, // AL,AH = AL*R8
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II<(ops R8:$src), "mul $src">;
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def MUL16r : I<0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize, // AX,DX = AX*R16
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II<(ops R16:$src), "mul $src">;
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def MUL32r : I<0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>, // EAX,EDX = EAX*R32
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II<(ops R32:$src), "mul $src">;
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def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8]
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def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16]
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def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32]
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// unsigned division/remainder
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def DIV8r : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
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def DIV16r : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
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def DIV32r : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
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def DIV8r : I<0xF6, MRM6r>, Imp<[AX],[AX]>, // AX/r8 = AL,AH
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II<(ops R8:$src), "div $src">;
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def DIV16r : I<0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize, // DX:AX/r16 = AX,DX
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II<(ops R16:$src), "div $src">;
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def DIV32r : I<0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>, // EDX:EAX/r32 = EAX,EDX
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II<(ops R32:$src), "div $src">;
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def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
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def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
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def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
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// signed division/remainder
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def IDIV8r : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH
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def IDIV16r: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX
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def IDIV32r: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX
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// Signed division/remainder.
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def IDIV8r : I<0xF6, MRM7r>, Imp<[AX],[AX]>, // AX/r8 = AL,AH
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II<(ops R8:$src), "idiv $src">;
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def IDIV16r: I<0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize, // DX:AX/r16 = AX,DX
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II<(ops R16:$src), "idiv $src">;
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def IDIV32r: I<0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>, // EDX:EAX/r32 = EAX,EDX
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II<(ops R32:$src), "idiv $src">;
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def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH
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def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX
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def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX
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||||
// Sign-extenders for division
|
||||
def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>, // AX = signext(AL)
|
||||
II<(ops), "cbw">;
|
||||
def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>, // DX:AX = signext(AX)
|
||||
II<(ops), "cwd">;
|
||||
def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>, // EDX:EAX = signext(EAX)
|
||||
II<(ops), "cdq">;
|
||||
// Sign-extenders for division.
|
||||
def CBW : I<0x98, RawFrm>, Imp<[AL],[AH]>, II<(ops), "cbw">; // AX = signext(AL)
|
||||
def CWD : I<0x99, RawFrm>, Imp<[AX],[DX]>, II<(ops), "cwd">; // DX:AX = signext(AX)
|
||||
def CDQ : I<0x99, RawFrm>, Imp<[EAX],[EDX]>, II<(ops), "cdq">; // EDX:EAX = signext(EAX)
|
||||
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Two address Instructions...
|
||||
@ -346,101 +351,137 @@ def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>, // EDX:EAX
|
||||
let isTwoAddress = 1 in {
|
||||
|
||||
// Conditional moves
|
||||
def CMOVB16rr : I <"cmovb", 0x42, MRMSrcReg>, TB, OpSize; // if <u, R16 = R16
|
||||
def CMOVB16rr : I<0x42, MRMSrcReg>, TB, OpSize, // if <u, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovb $dst, $src2">;
|
||||
def CMOVB16rm : Im16<"cmovb", 0x42, MRMSrcMem>, TB, OpSize; // if <u, R16 = [mem16]
|
||||
def CMOVB32rr : I <"cmovb", 0x42, MRMSrcReg>, TB; // if <u, R32 = R32
|
||||
def CMOVB32rr : I<0x42, MRMSrcReg>, TB, // if <u, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovb $dst, $src2">;
|
||||
def CMOVB32rm : Im32<"cmovb", 0x42, MRMSrcMem>, TB; // if <u, R32 = [mem32]
|
||||
|
||||
def CMOVAE16rr: I <"cmovae", 0x43, MRMSrcReg>, TB, OpSize; // if >=u, R16 = R16
|
||||
def CMOVAE16rr: I<0x43, MRMSrcReg>, TB, OpSize, // if >=u, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovae $dst, $src2">;
|
||||
def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16]
|
||||
def CMOVAE32rr: I <"cmovae", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32
|
||||
def CMOVAE32rr: I<0x43, MRMSrcReg>, TB, // if >=u, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovae $dst, $src2">;
|
||||
def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32]
|
||||
|
||||
def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16
|
||||
def CMOVE16rr : I<0x44, MRMSrcReg>, TB, OpSize, // if ==, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmove $dst, $src2">;
|
||||
def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16]
|
||||
def CMOVE32rr : I <"cmove", 0x44, MRMSrcReg>, TB; // if ==, R32 = R32
|
||||
def CMOVE32rr : I<0x44, MRMSrcReg>, TB, // if ==, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmove $dst, $src2">;
|
||||
def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32]
|
||||
|
||||
def CMOVNE16rr: I <"cmovne",0x45, MRMSrcReg>, TB, OpSize; // if !=, R16 = R16
|
||||
def CMOVNE16rr: I<0x45, MRMSrcReg>, TB, OpSize, // if !=, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovne $dst, $src2">;
|
||||
def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16]
|
||||
def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32
|
||||
def CMOVNE32rr: I<0x45, MRMSrcReg>, TB, // if !=, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovne $dst, $src2">;
|
||||
def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32]
|
||||
|
||||
def CMOVBE16rr: I <"cmovbe",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16
|
||||
def CMOVBE16rr: I<0x46, MRMSrcReg>, TB, OpSize, // if <=u, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovbe $dst, $src2">;
|
||||
def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16]
|
||||
def CMOVBE32rr: I <"cmovbe",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32
|
||||
def CMOVBE32rr: I<0x46, MRMSrcReg>, TB, // if <=u, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovbe $dst, $src2">;
|
||||
def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32]
|
||||
|
||||
def CMOVA16rr : I <"cmova", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16
|
||||
def CMOVA16rr : I<0x47, MRMSrcReg>, TB, OpSize, // if >u, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmova $dst, $src2">;
|
||||
def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16]
|
||||
def CMOVA32rr : I <"cmova", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32
|
||||
def CMOVA32rr : I<0x47, MRMSrcReg>, TB, // if >u, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmova $dst, $src2">;
|
||||
def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32]
|
||||
|
||||
def CMOVS16rr : I <"cmovs", 0x48, MRMSrcReg>, TB, OpSize; // if signed, R16 = R16
|
||||
def CMOVS16rr : I<0x48, MRMSrcReg>, TB, OpSize, // if signed, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovs $dst, $src2">;
|
||||
def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16]
|
||||
def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32
|
||||
def CMOVS32rr : I<0x48, MRMSrcReg>, TB, // if signed, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovs $dst, $src2">;
|
||||
def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32]
|
||||
|
||||
def CMOVNS16rr: I <"cmovns",0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16
|
||||
def CMOVNS16rr: I<0x49, MRMSrcReg>, TB, OpSize, // if !signed, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovns $dst, $src2">;
|
||||
def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16]
|
||||
def CMOVNS32rr: I <"cmovns",0x49, MRMSrcReg>, TB; // if !signed, R32 = R32
|
||||
def CMOVNS32rr: I<0x49, MRMSrcReg>, TB, // if !signed, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovns $dst, $src2">;
|
||||
def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32]
|
||||
|
||||
def CMOVL16rr : I <"cmovl", 0x4C, MRMSrcReg>, TB, OpSize; // if <s, R16 = R16
|
||||
def CMOVL16rr : I<0x4C, MRMSrcReg>, TB, OpSize, // if <s, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovl $dst, $src2">;
|
||||
def CMOVL16rm : Im16<"cmovl", 0x4C, MRMSrcMem>, TB, OpSize; // if <s, R16 = [mem16]
|
||||
def CMOVL32rr : I <"cmovl", 0x4C, MRMSrcReg>, TB; // if <s, R32 = R32
|
||||
def CMOVL32rr : I<0x4C, MRMSrcReg>, TB, // if <s, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovl $dst, $src2">;
|
||||
def CMOVL32rm : Im32<"cmovl", 0x4C, MRMSrcMem>, TB; // if <s, R32 = [mem32]
|
||||
|
||||
def CMOVGE16rr: I <"cmovge",0x4D, MRMSrcReg>, TB, OpSize; // if >=s, R16 = R16
|
||||
def CMOVGE16rr: I<0x4D, MRMSrcReg>, TB, OpSize, // if >=s, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovge $dst, $src2">;
|
||||
def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16]
|
||||
def CMOVGE32rr: I <"cmovge",0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32
|
||||
def CMOVGE32rr: I<0x4D, MRMSrcReg>, TB, // if >=s, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovge $dst, $src2">;
|
||||
def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32]
|
||||
|
||||
def CMOVLE16rr: I <"cmovle",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16
|
||||
def CMOVLE16rr: I<0x4E, MRMSrcReg>, TB, OpSize, // if <=s, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovle $dst, $src2">;
|
||||
def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16]
|
||||
def CMOVLE32rr: I <"cmovle",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32
|
||||
def CMOVLE32rr: I<0x4E, MRMSrcReg>, TB, // if <=s, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovle $dst, $src2">;
|
||||
def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32]
|
||||
|
||||
def CMOVG16rr : I <"cmovg", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16
|
||||
def CMOVG16rr : I<0x4F, MRMSrcReg>, TB, OpSize, // if >s, R16 = R16
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "cmovg $dst, $src2">;
|
||||
def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16]
|
||||
def CMOVG32rr : I <"cmovg", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32
|
||||
def CMOVG32rr : I<0x4F, MRMSrcReg>, TB, // if >s, R32 = R32
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "cmovg $dst, $src2">;
|
||||
def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32]
|
||||
|
||||
// unary instructions
|
||||
def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8
|
||||
def NEG16r : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16
|
||||
def NEG32r : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32
|
||||
def NEG8r : I<0xF6, MRM3r>, // R8 = -R8 = 0-R8
|
||||
II<(ops R8:$dst, R8:$src), "neg $dst">;
|
||||
def NEG16r : I<0xF7, MRM3r>, OpSize, // R16 = -R16 = 0-R16
|
||||
II<(ops R16:$dst, R16:$src), "neg $dst">;
|
||||
def NEG32r : I<0xF7, MRM3r>, // R32 = -R32 = 0-R32
|
||||
II<(ops R32:$dst, R32:$src), "neg $dst">;
|
||||
def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8]
|
||||
def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16]
|
||||
def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32]
|
||||
|
||||
def NOT8r : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1
|
||||
def NOT16r : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1
|
||||
def NOT32r : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1
|
||||
def NOT8r : I<0xF6, MRM2r>, // R8 = ~R8 = R8^-1
|
||||
II<(ops R8:$dst, R8:$src), "not $dst">;
|
||||
def NOT16r : I<0xF7, MRM2r>, OpSize, // R16 = ~R16 = R16^-1
|
||||
II<(ops R16:$dst, R16:$src), "not $dst">;
|
||||
def NOT32r : I<0xF7, MRM2r>, // R32 = ~R32 = R32^-1
|
||||
II<(ops R32:$dst, R32:$src), "not $dst">;
|
||||
def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1]
|
||||
def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1]
|
||||
def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1]
|
||||
|
||||
def INC8r : I <"inc", 0xFE, MRM0r>; // ++R8
|
||||
def INC16r : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16
|
||||
def INC32r : I <"inc", 0xFF, MRM0r>; // ++R32
|
||||
def INC8r : I<0xFE, MRM0r>, // ++R8
|
||||
II<(ops R8:$dst, R8:$src), "inc $dst">;
|
||||
def INC16r : I<0xFF, MRM0r>, OpSize, // ++R16
|
||||
II<(ops R16:$dst, R16:$src), "inc $dst">;
|
||||
def INC32r : I<0xFF, MRM0r>, // ++R32
|
||||
II<(ops R32:$dst, R32:$src), "inc $dst">;
|
||||
def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8
|
||||
def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16
|
||||
def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32
|
||||
|
||||
def DEC8r : I <"dec", 0xFE, MRM1r>; // --R8
|
||||
def DEC16r : I <"dec", 0xFF, MRM1r>, OpSize; // --R16
|
||||
def DEC32r : I <"dec", 0xFF, MRM1r>; // --R32
|
||||
def DEC8r : I<0xFE, MRM1r>, // --R8
|
||||
II<(ops R8:$dst, R8:$src), "dec $dst">;
|
||||
def DEC16r : I<0xFF, MRM1r>, OpSize, // --R16
|
||||
II<(ops R16:$dst, R16:$src), "dec $dst">;
|
||||
def DEC32r : I<0xFF, MRM1r>, // --R32
|
||||
II<(ops R32:$dst, R32:$src), "dec $dst">;
|
||||
def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8]
|
||||
def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16]
|
||||
def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32]
|
||||
|
||||
// Logical operators...
|
||||
def AND8rr : I <"and", 0x20, MRMDestReg>,
|
||||
def AND8rr : I<0x20, MRMDestReg>,
|
||||
II<(ops R8:$dst, R8:$src1, R8:$src2), "and $dst, $src2">;
|
||||
def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize,
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
|
||||
def AND32rr : I <"and", 0x21, MRMDestReg>,
|
||||
def AND16rr : I<0x21, MRMDestReg>, OpSize,
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "and $dst, $src2">;
|
||||
def AND32rr : I<0x21, MRMDestReg>,
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">;
|
||||
def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8
|
||||
def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16
|
||||
@ -462,9 +503,12 @@ def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8
|
||||
def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8
|
||||
|
||||
|
||||
def OR8rr : I <"or" , 0x08, MRMDestReg>;
|
||||
def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize;
|
||||
def OR32rr : I <"or" , 0x09, MRMDestReg>;
|
||||
def OR8rr : I<0x08, MRMDestReg>,
|
||||
II<(ops R8:$dst, R8:$src1, R8:$src2), "or $dst, $src2">;
|
||||
def OR16rr : I<0x09, MRMDestReg>, OpSize,
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "or $dst, $src2">;
|
||||
def OR32rr : I<0x09, MRMDestReg>,
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "or $dst, $src2">;
|
||||
def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8
|
||||
def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16
|
||||
def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32
|
||||
@ -485,9 +529,12 @@ def OR16mi8 : Im16i8<"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8
|
||||
def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8
|
||||
|
||||
|
||||
def XOR8rr : I <"xor", 0x30, MRMDestReg>;
|
||||
def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize;
|
||||
def XOR32rr : I <"xor", 0x31, MRMDestReg>;
|
||||
def XOR8rr : I<0x30, MRMDestReg>,
|
||||
II<(ops R8:$dst, R8:$src1, R8:$src2), "xor $dst, $src2">;
|
||||
def XOR16rr : I<0x31, MRMDestReg>, OpSize,
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "xor $dst, $src2">;
|
||||
def XOR32rr : I<0x31, MRMDestReg>,
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "xor $dst, $src2">;
|
||||
def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8
|
||||
def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16
|
||||
def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32
|
||||
@ -510,11 +557,11 @@ def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8
|
||||
// Shift instructions
|
||||
// FIXME: provide shorter instructions when imm8 == 1
|
||||
let Uses = [CL], printImplicitUsesAfter = 1 in {
|
||||
def SHL8rCL : I <"shl", 0xD2, MRM4r > , // R8 <<= cl
|
||||
def SHL8rCL : I<0xD2, MRM4r> , // R8 <<= cl
|
||||
II<(ops R8:$dst, R8:$src), "shl $dst, %CL">;
|
||||
def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, // R16 <<= cl
|
||||
def SHL16rCL : I<0xD3, MRM4r>, OpSize, // R16 <<= cl
|
||||
II<(ops R16:$dst, R16:$src), "shl $dst, %CL">;
|
||||
def SHL32rCL : I <"shl", 0xD3, MRM4r > , // R32 <<= cl
|
||||
def SHL32rCL : I<0xD3, MRM4r> , // R32 <<= cl
|
||||
II<(ops R32:$dst, R32:$src), "shl $dst, %CL">;
|
||||
def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > ; // [mem8] <<= cl
|
||||
def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize; // [mem16] <<= cl
|
||||
@ -529,11 +576,11 @@ def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= i
|
||||
def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8
|
||||
|
||||
let Uses = [CL], printImplicitUsesAfter = 1 in {
|
||||
def SHR8rCL : I <"shr", 0xD2, MRM5r > , // R8 >>= cl
|
||||
def SHR8rCL : I<0xD2, MRM5r> , // R8 >>= cl
|
||||
II<(ops R8:$dst, R8:$src), "shr $dst, %CL">;
|
||||
def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, // R16 >>= cl
|
||||
def SHR16rCL : I<0xD3, MRM5r>, OpSize, // R16 >>= cl
|
||||
II<(ops R16:$dst, R16:$src), "shr $dst, %CL">;
|
||||
def SHR32rCL : I <"shr", 0xD3, MRM5r > , // R32 >>= cl
|
||||
def SHR32rCL : I<0xD3, MRM5r> , // R32 >>= cl
|
||||
II<(ops R32:$dst, R32:$src), "shr $dst, %CL">;
|
||||
def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > ; // [mem8] >>= cl
|
||||
def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize; // [mem16] >>= cl
|
||||
@ -548,11 +595,11 @@ def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= i
|
||||
def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8
|
||||
|
||||
let Uses = [CL], printImplicitUsesAfter = 1 in {
|
||||
def SAR8rCL : I <"sar", 0xD2, MRM7r >, // R8 >>>= cl
|
||||
def SAR8rCL : I<0xD2, MRM7r>, // R8 >>>= cl
|
||||
II<(ops R8:$dst, R8:$src), "sar $dst, %CL">;
|
||||
def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, // R16 >>>= cl
|
||||
def SAR16rCL : I<0xD3, MRM7r>, OpSize, // R16 >>>= cl
|
||||
II<(ops R16:$dst, R16:$src), "sar $dst, %CL">;
|
||||
def SAR32rCL : I <"sar", 0xD3, MRM7r >, // R32 >>>= cl
|
||||
def SAR32rCL : I<0xD3, MRM7r>, // R32 >>>= cl
|
||||
II<(ops R32:$dst, R32:$src), "sar $dst, %CL">;
|
||||
def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > ; // [mem8] >>>= cl
|
||||
def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize; // [mem16] >>>= cl
|
||||
@ -567,11 +614,11 @@ def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>=
|
||||
def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8
|
||||
|
||||
let Uses = [CL], printImplicitUsesAfter = 1 in {
|
||||
def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, // R32 <<= R32,R32 cl
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "shld $dst, $src2, %CL">;
|
||||
def SHLD32rrCL : I<0xA5, MRMDestReg>, TB, // R32 <<= R32,R32 cl
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "shld $dst, $src2, %CL">;
|
||||
def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 cl
|
||||
def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, // R32 >>= R32,R32 cl
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "shrd $dst, $src2, %CL">;
|
||||
def SHRD32rrCL : I<0xAD, MRMDestReg>, TB, // R32 >>= R32,R32 cl
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "shrd $dst, $src2, %CL">;
|
||||
def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 cl
|
||||
}
|
||||
|
||||
@ -582,9 +629,9 @@ def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>=
|
||||
|
||||
|
||||
// Arithmetic...
|
||||
def ADD8rr : I <"add", 0x00, MRMDestReg>;
|
||||
def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize;
|
||||
def ADD32rr : I <"add", 0x01, MRMDestReg>;
|
||||
def ADD8rr : I<0x00, MRMDestReg>, II<(ops R8:$dst, R8:$src1, R8:$src2), "add $dst, $src2">;
|
||||
def ADD16rr : I<0x01, MRMDestReg>, OpSize, II<(ops R16:$dst, R16:$src1, R16:$src2), "add $dst, $src2">;
|
||||
def ADD32rr : I<0x01, MRMDestReg>, II<(ops R32:$dst, R32:$src1, R32:$src2), "add $dst, $src2">;
|
||||
def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8
|
||||
def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16
|
||||
def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32
|
||||
@ -604,7 +651,8 @@ def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >;
|
||||
def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8
|
||||
def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8
|
||||
|
||||
def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry
|
||||
def ADC32rr : I<0x11, MRMDestReg>, // R32 += R32+Carry
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">;
|
||||
def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry
|
||||
def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry
|
||||
def ADC32ri : Ii32 <"adc", 0x81, MRM2r >; // R32 += I32+Carry
|
||||
@ -612,9 +660,9 @@ def ADC32ri8 : Ii8 <"adc", 0x83, MRM2r >; // R32 += I8+Carry
|
||||
def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry
|
||||
def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry
|
||||
|
||||
def SUB8rr : I <"sub", 0x28, MRMDestReg>;
|
||||
def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize;
|
||||
def SUB32rr : I <"sub", 0x29, MRMDestReg>;
|
||||
def SUB8rr : I<0x28, MRMDestReg>, II<(ops R8:$dst, R8:$src1, R8:$src2), "sub $dst, $src2">;
|
||||
def SUB16rr : I<0x29, MRMDestReg>, OpSize, II<(ops R16:$dst, R16:$src1, R16:$src2), "sub $dst, $src2">;
|
||||
def SUB32rr : I<0x29, MRMDestReg>, II<(ops R32:$dst, R32:$src1, R32:$src2), "sub $dst, $src2">;
|
||||
def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8
|
||||
def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16
|
||||
def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32
|
||||
@ -634,7 +682,8 @@ def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >;
|
||||
def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8
|
||||
def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8
|
||||
|
||||
def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry
|
||||
def SBB32rr : I<0x19, MRMDestReg>, // R32 -= R32+Carry
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "adc $dst, $src2">;
|
||||
def SBB32mr : Im32 <"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry
|
||||
def SBB32rm : Im32 <"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry
|
||||
def SBB32ri : Ii32 <"sbb", 0x81, MRM3r >; // R32 -= I32+Carry
|
||||
@ -642,8 +691,10 @@ def SBB32ri8 : Ii8 <"sbb", 0x83, MRM3r >; // R32 -= I8+Carry
|
||||
def SBB32mi : Im32i32<"sbb", 0x81, MRM3m >; // [mem32] -= I32+Carry
|
||||
def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m >; // [mem32] -= I8+Carry
|
||||
|
||||
def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize;
|
||||
def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB;
|
||||
def IMUL16rr : I<0xAF, MRMSrcReg>, TB, OpSize,
|
||||
II<(ops R16:$dst, R16:$src1, R16:$src2), "imul $dst, $src2">;
|
||||
def IMUL32rr : I<0xAF, MRMSrcReg>, TB,
|
||||
II<(ops R32:$dst, R32:$src1, R32:$src2), "imul $dst, $src2">;
|
||||
def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize;
|
||||
def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ;
|
||||
|
||||
@ -661,9 +712,12 @@ def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Test instructions are just like AND, except they don't generate a result.
|
||||
def TEST8rr : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8
|
||||
def TEST16rr : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16
|
||||
def TEST32rr : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32
|
||||
def TEST8rr : I<0x84, MRMDestReg>, // flags = R8 & R8
|
||||
II<(ops R8:$src1, R8:$src2), "test $src1, $src2">;
|
||||
def TEST16rr : I<0x85, MRMDestReg>, OpSize, // flags = R16 & R16
|
||||
II<(ops R16:$src1, R16:$src2), "test $src1, $src2">;
|
||||
def TEST32rr : I<0x85, MRMDestReg>, // flags = R32 & R32
|
||||
II<(ops R32:$src1, R32:$src2), "test $src1, $src2">;
|
||||
def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8
|
||||
def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16
|
||||
def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32
|
||||
@ -681,42 +735,58 @@ def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] &
|
||||
|
||||
|
||||
// Condition code ops, incl. set if equal/not equal/...
|
||||
def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH
|
||||
II<(ops), "sahf">;
|
||||
def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags
|
||||
II<(ops), "lahf">;
|
||||
def SAHF : I<0x9E, RawFrm>, Imp<[AH],[]>, // flags = AH
|
||||
II<(ops), "sahf">;
|
||||
def LAHF : I<0x9F, RawFrm>, Imp<[],[AH]>, // AH = flags
|
||||
II<(ops), "lahf">;
|
||||
|
||||
def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign
|
||||
def SETBr : I<0x92, MRM0r>, TB, // R8 = < unsign
|
||||
II<(ops R8:$dst), "setb $dst">;
|
||||
def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign
|
||||
def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign
|
||||
def SETAEr : I<0x93, MRM0r>, TB, // R8 = >= unsign
|
||||
II<(ops R8:$dst), "setae $dst">;
|
||||
def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign
|
||||
def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = ==
|
||||
def SETEr : I<0x94, MRM0r>, TB, // R8 = ==
|
||||
II<(ops R8:$dst), "sete $dst">;
|
||||
def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = ==
|
||||
def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = !=
|
||||
def SETNEr : I<0x95, MRM0r>, TB, // R8 = !=
|
||||
II<(ops R8:$dst), "setne $dst">;
|
||||
def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = !=
|
||||
def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign
|
||||
def SETBEr : I<0x96, MRM0r>, TB, // R8 = <= unsign
|
||||
II<(ops R8:$dst), "setbe $dst">;
|
||||
def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign
|
||||
def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed
|
||||
def SETAr : I<0x97, MRM0r>, TB, // R8 = > signed
|
||||
II<(ops R8:$dst), "seta $dst">;
|
||||
def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed
|
||||
def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = <sign bit>
|
||||
def SETSr : I<0x98, MRM0r>, TB, // R8 = <sign bit>
|
||||
II<(ops R8:$dst), "sets $dst">;
|
||||
def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = <sign bit>
|
||||
def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = !<sign bit>
|
||||
def SETNSr : I<0x99, MRM0r>, TB, // R8 = !<sign bit>
|
||||
II<(ops R8:$dst), "setns $dst">;
|
||||
def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = !<sign bit>
|
||||
def SETPr : I <"setp" , 0x9A, MRM0r>, TB; // R8 = parity
|
||||
def SETPr : I<0x9A, MRM0r>, TB, // R8 = parity
|
||||
II<(ops R8:$dst), "setp $dst">;
|
||||
def SETPm : Im8<"setp" , 0x9A, MRM0m>, TB; // [mem8] = parity
|
||||
def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed
|
||||
def SETLr : I<0x9C, MRM0r>, TB, // R8 = < signed
|
||||
II<(ops R8:$dst), "setl $dst">;
|
||||
def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed
|
||||
def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed
|
||||
def SETGEr : I<0x9D, MRM0r>, TB, // R8 = >= signed
|
||||
II<(ops R8:$dst), "setge $dst">;
|
||||
def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed
|
||||
def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed
|
||||
def SETLEr : I<0x9E, MRM0r>, TB, // R8 = <= signed
|
||||
II<(ops R8:$dst), "setle $dst">;
|
||||
def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed
|
||||
def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed
|
||||
def SETGr : I<0x9F, MRM0r>, TB, // R8 = < signed
|
||||
II<(ops R8:$dst), "setg $dst">;
|
||||
def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed
|
||||
|
||||
// Integer comparisons
|
||||
def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8
|
||||
def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16
|
||||
def CMP32rr : I <"cmp", 0x39, MRMDestReg>; // compare R32, R32
|
||||
def CMP8rr : I<0x38, MRMDestReg>, // compare R8, R8
|
||||
II<(ops R8:$src1, R8:$src2), "cmp $src1, $src2">;
|
||||
def CMP16rr : I<0x39, MRMDestReg>, OpSize, // compare R16, R16
|
||||
II<(ops R16:$src1, R16:$src2), "cmp $src1, $src2">;
|
||||
def CMP32rr : I<0x39, MRMDestReg>, // compare R32, R32
|
||||
II<(ops R32:$src1, R32:$src2), "cmp $src1, $src2">;
|
||||
def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8
|
||||
def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16
|
||||
def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32
|
||||
@ -731,16 +801,22 @@ def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], i
|
||||
def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32
|
||||
|
||||
// Sign/Zero extenders
|
||||
def MOVSX16rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8)
|
||||
def MOVSX32rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8)
|
||||
def MOVSX32rr16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16)
|
||||
def MOVSX16rr8 : I<0xBE, MRMSrcReg>, TB, OpSize, // R16 = signext(R8)
|
||||
II<(ops R16:$dst, R8:$src), "movsx $dst, $src">;
|
||||
def MOVSX32rr8 : I<0xBE, MRMSrcReg>, TB, // R32 = signext(R8)
|
||||
II<(ops R32:$dst, R8:$src), "movsx $dst, $src">;
|
||||
def MOVSX32rr16: I<0xBF, MRMSrcReg>, TB, // R32 = signext(R16)
|
||||
II<(ops R32:$dst, R16:$src), "movsx $dst, $src">;
|
||||
def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8])
|
||||
def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8])
|
||||
def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16])
|
||||
|
||||
def MOVZX16rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8)
|
||||
def MOVZX32rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8)
|
||||
def MOVZX32rr16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16)
|
||||
def MOVZX16rr8 : I<0xB6, MRMSrcReg>, TB, OpSize, // R16 = zeroext(R8)
|
||||
II<(ops R16:$dst, R8:$src), "movzx $dst, $src">;
|
||||
def MOVZX32rr8 : I<0xB6, MRMSrcReg>, TB, // R32 = zeroext(R8)
|
||||
II<(ops R32:$dst, R8:$src), "movzx $dst, $src">;
|
||||
def MOVZX32rr16: I<0xB7, MRMSrcReg>, TB, // R32 = zeroext(R16)
|
||||
II<(ops R32:$dst, R16:$src), "movzx $dst, $src">;
|
||||
def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8])
|
||||
def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8])
|
||||
def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16])
|
||||
@ -769,14 +845,14 @@ class FPI80m<string n, bits<8> o, Format F, FPFormat fp> : FPIM<n, o, F, fp, Mem
|
||||
// because they can be expanded by the fp spackifier into one of many different
|
||||
// forms of instructions for doing these operations. Until the stackifier runs,
|
||||
// we prefer to be abstract.
|
||||
def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2
|
||||
def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
|
||||
def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
|
||||
def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
|
||||
def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
|
||||
def FpMOV : FPI<"", 0, Pseudo, SpecialFP>; // f1 = fmov f2
|
||||
def FpADD : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3
|
||||
def FpSUB : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3
|
||||
def FpMUL : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3
|
||||
def FpDIV : FPI<"", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3
|
||||
|
||||
def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0)
|
||||
def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR
|
||||
def FpGETRESULT : FPI<"",0, Pseudo, SpecialFP>; // FPR = ST(0)
|
||||
def FpSETRESULT : FPI<"",0, Pseudo, SpecialFP>; // ST(0) = FPR
|
||||
|
||||
// FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem]
|
||||
def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real]
|
||||
@ -819,17 +895,17 @@ def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int
|
||||
|
||||
// Floating point cmovs...
|
||||
let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in {
|
||||
def FCMOVB : FPI<"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0)
|
||||
def FCMOVB : FPI<"" , 0xC0, AddRegFrm, CondMovFP>, DA, // fcmovb ST(i) -> ST(0)
|
||||
II<(ops RST:$op), "fcmovb %ST(0), $op">;
|
||||
def FCMOVBE : FPI<"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0)
|
||||
def FCMOVBE : FPI<"", 0xD0, AddRegFrm, CondMovFP>, DA, // fcmovbe ST(i) -> ST(0)
|
||||
II<(ops RST:$op), "fcmovbe %ST(0), $op">;
|
||||
def FCMOVE : FPI<"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0)
|
||||
def FCMOVE : FPI<"" , 0xC8, AddRegFrm, CondMovFP>, DA, // fcmove ST(i) -> ST(0)
|
||||
II<(ops RST:$op), "fcmove %ST(0), $op">;
|
||||
def FCMOVAE : FPI<"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0)
|
||||
def FCMOVAE : FPI<"", 0xC0, AddRegFrm, CondMovFP>, DB, // fcmovae ST(i) -> ST(0)
|
||||
II<(ops RST:$op), "fcmovae %ST(0), $op">;
|
||||
def FCMOVA : FPI<"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0)
|
||||
def FCMOVA : FPI<"" , 0xD0, AddRegFrm, CondMovFP>, DB, // fcmova ST(i) -> ST(0)
|
||||
II<(ops RST:$op), "fcmova %ST(0), $op">;
|
||||
def FCMOVNE : FPI<"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0)
|
||||
def FCMOVNE : FPI<"", 0xC8, AddRegFrm, CondMovFP>, DB, // fcmovne ST(i) -> ST(0)
|
||||
II<(ops RST:$op), "fcmovne %ST(0), $op">;
|
||||
}
|
||||
|
||||
@ -859,70 +935,72 @@ def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store sig
|
||||
def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0)
|
||||
|
||||
// Floating point constant loads...
|
||||
def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9,
|
||||
def FLD0 : FPI<"", 0xEE, RawFrm, ZeroArgFP>, D9,
|
||||
II<(ops), "fldz">;
|
||||
def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9,
|
||||
def FLD1 : FPI<"", 0xE8, RawFrm, ZeroArgFP>, D9,
|
||||
II<(ops), "fld1">;
|
||||
|
||||
|
||||
// Unary operations...
|
||||
def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2
|
||||
def FCHS : FPI<"", 0xE0, RawFrm, OneArgFPRW>, D9, // f1 = fchs f2
|
||||
II<(ops), "fchs">;
|
||||
def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0)
|
||||
def FTST : FPI<"", 0xE4, RawFrm, OneArgFP>, D9, // ftst ST(0)
|
||||
II<(ops), "ftst">;
|
||||
|
||||
// Binary arithmetic operations...
|
||||
class FPST0rInst<string n, bits<8> o> : I<n, o, AddRegFrm>, D8 {
|
||||
class FPST0rInst<bits<8> o> : I<o, AddRegFrm>, D8 {
|
||||
list<Register> Uses = [ST0];
|
||||
list<Register> Defs = [ST0];
|
||||
}
|
||||
class FPrST0Inst<string n, bits<8> o> : I<n, o, AddRegFrm>, DC {
|
||||
class FPrST0Inst<bits<8> o> : I<o, AddRegFrm>, DC {
|
||||
list<Register> Uses = [ST0];
|
||||
}
|
||||
class FPrST0PInst<string n, bits<8> o> : I<n, o, AddRegFrm>, DE {
|
||||
class FPrST0PInst<bits<8> o> : I<o, AddRegFrm>, DE {
|
||||
list<Register> Uses = [ST0];
|
||||
}
|
||||
|
||||
def FADDST0r : FPST0rInst <"fadd", 0xC0>;
|
||||
def FADDrST0 : FPrST0Inst <"fadd", 0xC0>, II<(ops RST:$op), "fadd $op, %ST(0)">;
|
||||
def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>;
|
||||
def FADDST0r : FPST0rInst <0xC0>, II<(ops RST:$op), "fadd $op">;
|
||||
def FADDrST0 : FPrST0Inst <0xC0>, II<(ops RST:$op), "fadd $op, %ST(0)">;
|
||||
def FADDPrST0 : FPrST0PInst<0xC0>, II<(ops RST:$op), "faddp $op">;
|
||||
|
||||
def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>;
|
||||
def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>, II<(ops RST:$op), "fsub $op, %ST(0)">;
|
||||
def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>;
|
||||
def FSUBRST0r : FPST0rInst <0xE8>, II<(ops RST:$op), "fsubr $op">;
|
||||
def FSUBrST0 : FPrST0Inst <0xE8>, II<(ops RST:$op), "fsub $op, %ST(0)">;
|
||||
def FSUBPrST0 : FPrST0PInst<0xE8>, II<(ops RST:$op), "fsubp $op">;
|
||||
|
||||
def FSUBST0r : FPST0rInst <"fsub", 0xE0>;
|
||||
def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>, II<(ops RST:$op), "fsubr $op, %ST(0)">;
|
||||
def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>;
|
||||
def FSUBST0r : FPST0rInst <0xE0>, II<(ops RST:$op), "fsub $op">;
|
||||
def FSUBRrST0 : FPrST0Inst <0xE0>, II<(ops RST:$op), "fsubr $op, %ST(0)">;
|
||||
def FSUBRPrST0 : FPrST0PInst<0xE0>, II<(ops RST:$op), "fsubrp $op">;
|
||||
|
||||
def FMULST0r : FPST0rInst <"fmul", 0xC8>;
|
||||
def FMULrST0 : FPrST0Inst <"fmul", 0xC8>, II<(ops RST:$op), "fmul $op, %ST(0)">;
|
||||
def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>;
|
||||
def FMULST0r : FPST0rInst <0xC8>, II<(ops RST:$op), "fmul $op">;
|
||||
def FMULrST0 : FPrST0Inst <0xC8>, II<(ops RST:$op), "fmul $op, %ST(0)">;
|
||||
def FMULPrST0 : FPrST0PInst<0xC8>, II<(ops RST:$op), "fmulp $op">;
|
||||
|
||||
def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>;
|
||||
def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>, II<(ops RST:$op), "fdiv $op, %ST(0)">;
|
||||
def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>;
|
||||
def FDIVRST0r : FPST0rInst <0xF8>, II<(ops RST:$op), "fdivr $op">;
|
||||
def FDIVrST0 : FPrST0Inst <0xF8>, II<(ops RST:$op), "fdiv $op, %ST(0)">;
|
||||
def FDIVPrST0 : FPrST0PInst<0xF8>, II<(ops RST:$op), "fdivp $op">;
|
||||
|
||||
def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i)
|
||||
def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>, II<(ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i)
|
||||
def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop
|
||||
def FDIVST0r : FPST0rInst <0xF0>, II<(ops RST:$op), "fdiv $op">; // ST(0) = ST(0) / ST(i)
|
||||
def FDIVRrST0 : FPrST0Inst <0xF0>, II<(ops RST:$op), "fdivr $op, %ST(0)">; // ST(i) = ST(0) / ST(i)
|
||||
def FDIVRPrST0 : FPrST0PInst<0xF0>, II<(ops RST:$op), "fdivrp $op">; // ST(i) = ST(0) / ST(i), pop
|
||||
|
||||
// Floating point compares
|
||||
def FUCOMr : FPI<"fucom", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i)
|
||||
def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop
|
||||
def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop
|
||||
def FUCOMr : FPI<"", 0xE0, AddRegFrm, CompareFP>, DD, Imp<[ST0],[]>, // FPSW = compare ST(0) with ST(i)
|
||||
II<(ops RST:$reg), "fucom $reg">;
|
||||
def FUCOMPr : I<0xE8, AddRegFrm>, DD, Imp<[ST0],[]>, // FPSW = compare ST(0) with ST(i), pop
|
||||
II<(ops RST:$reg), "fucomp $reg">;
|
||||
def FUCOMPPr : I<0xE9, RawFrm >, DA, Imp<[ST0],[]>, // compare ST(0) with ST(1), pop, pop
|
||||
II<(ops), "fucompp">;
|
||||
|
||||
|
||||
def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i)
|
||||
def FUCOMIr : FPI<"", 0xE8, AddRegFrm, CompareFP>, DB, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i)
|
||||
II<(ops RST:$reg), "fucomi %ST(0), $reg">;
|
||||
def FUCOMIPr : I<"fucomip", 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i), pop
|
||||
def FUCOMIPr : I<0xE8, AddRegFrm>, DF, Imp<[ST0],[]>, // CC = compare ST(0) with ST(i), pop
|
||||
II<(ops RST:$reg), "fucomip %ST(0), $reg">;
|
||||
|
||||
|
||||
// Floating point flag ops
|
||||
def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags
|
||||
def FNSTSW8r : I<0xE0, RawFrm>, DF, Imp<[],[AX]>, // AX = fp flags
|
||||
II<(ops), "fnstsw">;
|
||||
|
||||
def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world
|
||||
def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16]
|
||||
def FNSTCW16m : Im16<"fnstcw", 0xD9, MRM7m>; // [mem16] = X87 control world
|
||||
def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m>; // X87 control world = [mem16]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user