mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
[SparcV9] Handle i64 <-> float conversions in sparcv9 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193957 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju
parent
0c7ba3cef2
commit
fcd5e86396
@ -949,9 +949,10 @@ static bool isFP128ABICall(const char *CalleeName)
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{ "_Q_add", "_Q_sub", "_Q_mul", "_Q_div",
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"_Q_sqrt", "_Q_neg",
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"_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq",
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"_Q_lltoq", "_Q_ulltoq",
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0
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};
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for (const char * const *I = ABICalls; I != 0; ++I)
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for (const char * const *I = ABICalls; *I != 0; ++I)
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if (strcmp(CalleeName, *I) == 0)
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return true;
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return false;
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@ -1341,7 +1342,7 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SREM, MVT::i32, Expand);
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setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
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setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
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// ... nor does SparcV9.
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if (Subtarget->is64Bit()) {
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setOperationAction(ISD::UREM, MVT::i64, Expand);
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@ -1353,10 +1354,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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// Custom expand fp<->sint
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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// Custom Expand fp<->uint
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::BITCAST, MVT::f32, Expand);
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setOperationAction(ISD::BITCAST, MVT::i32, Expand);
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@ -1497,6 +1502,14 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setOperationAction(ISD::FNEG, MVT::f128, Custom);
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setOperationAction(ISD::FABS, MVT::f128, Custom);
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}
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if (!Subtarget->is64Bit()) {
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setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
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setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
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setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
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setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
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}
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} else {
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// Custom legalize f128 operations.
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@ -1523,6 +1536,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
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setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
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setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
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setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
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setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
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setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
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setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
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setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
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setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
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setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
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@ -1537,6 +1554,10 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
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setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
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setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
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setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq");
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setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll");
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setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull");
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setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq");
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setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq");
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setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq");
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setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq");
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setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos");
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@ -1564,6 +1585,8 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case SPISD::Lo: return "SPISD::Lo";
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case SPISD::FTOI: return "SPISD::FTOI";
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case SPISD::ITOF: return "SPISD::ITOF";
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case SPISD::FTOX: return "SPISD::FTOX";
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case SPISD::XTOF: return "SPISD::XTOF";
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case SPISD::CALL: return "SPISD::CALL";
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case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
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case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
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@ -2055,59 +2078,97 @@ static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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// Convert the fp value to integer in an FP register.
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assert(Op.getValueType() == MVT::i32);
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EVT VT = Op.getValueType();
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assert(VT == MVT::i32 || VT == MVT::i64);
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if (Op.getOperand(0).getValueType() == MVT::f128 && !hasHardQuad)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPTOSINT_F128_I32), 1);
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// Expand f128 operations to fp128 abi calls.
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if (Op.getOperand(0).getValueType() == MVT::f128
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&& (!hasHardQuad || !TLI.isTypeLegal(VT))) {
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const char *libName = TLI.getLibcallName(VT == MVT::i32
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? RTLIB::FPTOSINT_F128_I32
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: RTLIB::FPTOSINT_F128_I64);
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return TLI.LowerF128Op(Op, DAG, libName, 1);
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}
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Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
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return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
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// Expand if the resulting type is illegal.
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if (!TLI.isTypeLegal(VT))
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return SDValue(0, 0);
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// Otherwise, Convert the fp value to integer in an FP register.
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if (VT == MVT::i32)
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Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
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else
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Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0));
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return DAG.getNode(ISD::BITCAST, dl, VT, Op);
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}
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static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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assert(Op.getOperand(0).getValueType() == MVT::i32);
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SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
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// Convert the int value to FP in an FP register.
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if (Op.getValueType() == MVT::f128 && !hasHardQuad)
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::SINTTOFP_I32_F128), 1);
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return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
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EVT OpVT = Op.getOperand(0).getValueType();
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assert(OpVT == MVT::i32 || (OpVT == MVT::i64));
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EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64;
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// Expand f128 operations to fp128 ABI calls.
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if (Op.getValueType() == MVT::f128
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&& (!hasHardQuad || !TLI.isTypeLegal(OpVT))) {
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const char *libName = TLI.getLibcallName(OpVT == MVT::i32
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? RTLIB::SINTTOFP_I32_F128
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: RTLIB::SINTTOFP_I64_F128);
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return TLI.LowerF128Op(Op, DAG, libName, 1);
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}
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// Expand if the operand type is illegal.
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if (!TLI.isTypeLegal(OpVT))
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return SDValue(0, 0);
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// Otherwise, Convert the int value to FP in an FP register.
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SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0));
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unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF;
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return DAG.getNode(opcode, dl, Op.getValueType(), Tmp);
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}
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static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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EVT VT = Op.getValueType();
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// Expand if it does not involve f128 or the target has support for
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// quad floating point instructions.
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if (Op.getOperand(0).getValueType() != MVT::f128 || hasHardQuad)
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// quad floating point instructions and the resulting type is legal.
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if (Op.getOperand(0).getValueType() != MVT::f128 ||
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(hasHardQuad && TLI.isTypeLegal(VT)))
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return SDValue(0, 0);
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SDLoc dl(Op);
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assert(Op.getValueType() == MVT::i32);
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assert(VT == MVT::i32 || VT == MVT::i64);
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::FPTOUINT_F128_I32), 1);
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TLI.getLibcallName(VT == MVT::i32
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? RTLIB::FPTOUINT_F128_I32
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: RTLIB::FPTOUINT_F128_I64),
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1);
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}
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static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG,
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const SparcTargetLowering &TLI,
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bool hasHardQuad) {
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SDLoc dl(Op);
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EVT OpVT = Op.getOperand(0).getValueType();
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assert(OpVT == MVT::i32 || OpVT == MVT::i64);
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// Expand if it does not involve f128 or the target has support for
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// quad floating point instructions.
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if (Op.getValueType() != MVT::f128 || hasHardQuad)
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// quad floating point instructions and the operand type is legal.
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if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT)))
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return SDValue(0, 0);
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SDLoc dl(Op);
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assert(Op.getOperand(0).getValueType() == MVT::i32);
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return TLI.LowerF128Op(Op, DAG,
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TLI.getLibcallName(RTLIB::UINTTOFP_I32_F128), 1);
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TLI.getLibcallName(OpVT == MVT::i32
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? RTLIB::UINTTOFP_I32_F128
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: RTLIB::UINTTOFP_I64_F128),
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1);
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}
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static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
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@ -2702,3 +2763,50 @@ SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
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// The Sparc target isn't yet aware of offsets.
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return false;
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}
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void SparcTargetLowering::ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>& Results,
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SelectionDAG &DAG) const {
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SDLoc dl(N);
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RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL;
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switch (N->getOpcode()) {
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default:
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llvm_unreachable("Do not know how to custom type legalize this operation!");
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT:
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// Custom lower only if it involves f128 or i64.
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if (N->getOperand(0).getValueType() != MVT::f128
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|| N->getValueType(0) != MVT::i64)
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return;
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libCall = ((N->getOpcode() == ISD::FP_TO_SINT)
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? RTLIB::FPTOSINT_F128_I64
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: RTLIB::FPTOUINT_F128_I64);
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Results.push_back(LowerF128Op(SDValue(N, 0),
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DAG,
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getLibcallName(libCall),
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1));
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return;
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case ISD::SINT_TO_FP:
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case ISD::UINT_TO_FP:
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// Custom lower only if it involves f128 or i64.
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if (N->getValueType(0) != MVT::f128
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|| N->getOperand(0).getValueType() != MVT::i64)
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return;
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libCall = ((N->getOpcode() == ISD::SINT_TO_FP)
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? RTLIB::SINTTOFP_I64_F128
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: RTLIB::UINTTOFP_I64_F128);
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Results.push_back(LowerF128Op(SDValue(N, 0),
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DAG,
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getLibcallName(libCall),
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1));
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return;
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}
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}
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@ -37,6 +37,8 @@ namespace llvm {
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FTOI, // FP to Int within a FP register.
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ITOF, // Int to FP within a FP register.
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FTOX, // FP to Int64 within a FP register.
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XTOF, // Int64 to FP within a FP register.
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CALL, // A call instruction.
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RET_FLAG, // Return with a flag operand.
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@ -149,6 +151,10 @@ namespace llvm {
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// (ldd, call _Q_fdtoq) is more expensive than two ldds.
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return VT != MVT::f128;
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}
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virtual void ReplaceNodeResults(SDNode *N,
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SmallVectorImpl<SDValue>& Results,
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SelectionDAG &DAG) const;
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};
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} // end namespace llvm
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@ -344,6 +344,42 @@ def FMOVD_XCC : Pseudo<(outs DFPRegs:$rd),
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(SPselectxcc f64:$rs2, f64:$f, imm:$cond))]>;
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} // Uses, Constraints
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//===----------------------------------------------------------------------===//
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// 64-bit Floating Point Conversions.
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//===----------------------------------------------------------------------===//
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let Predicates = [Is64Bit] in {
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def FXTOS : F3_3u<2, 0b110100, 0b010000100,
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(outs FPRegs:$dst), (ins DFPRegs:$src),
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"fxtos $src, $dst",
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[(set FPRegs:$dst, (SPxtof DFPRegs:$src))]>;
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def FXTOD : F3_3u<2, 0b110100, 0b010001000,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fxtod $src, $dst",
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[(set DFPRegs:$dst, (SPxtof DFPRegs:$src))]>;
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def FXTOQ : F3_3u<2, 0b110100, 0b010001100,
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(outs QFPRegs:$dst), (ins DFPRegs:$src),
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"fxtoq $src, $dst",
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[(set QFPRegs:$dst, (SPxtof DFPRegs:$src))]>,
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Requires<[HasHardQuad]>;
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def FSTOX : F3_3u<2, 0b110100, 0b010000001,
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(outs DFPRegs:$dst), (ins FPRegs:$src),
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"fstox $src, $dst",
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[(set DFPRegs:$dst, (SPftox FPRegs:$src))]>;
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def FDTOX : F3_3u<2, 0b110100, 0b010000010,
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(outs DFPRegs:$dst), (ins DFPRegs:$src),
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"fdtox $src, $dst",
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[(set DFPRegs:$dst, (SPftox DFPRegs:$src))]>;
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def FQTOX : F3_3u<2, 0b110100, 0b010000011,
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(outs DFPRegs:$dst), (ins QFPRegs:$src),
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"fqtox $src, $dst",
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[(set DFPRegs:$dst, (SPftox QFPRegs:$src))]>,
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Requires<[HasHardQuad]>;
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} // Predicates = [Is64Bit]
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def : Pat<(SPselectxcc i64:$t, i64:$f, imm:$cond),
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(MOVXCCrr $t, $f, imm:$cond)>;
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def : Pat<(SPselectxcc (i64 simm11:$t), i64:$f, imm:$cond),
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@ -107,6 +107,10 @@ def SDTSPFTOI :
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SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
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def SDTSPITOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
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def SDTSPFTOX :
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SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
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def SDTSPXTOF :
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SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
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def SDTSPtlsadd :
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SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
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@ -124,6 +128,8 @@ def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
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def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
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def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
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def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
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def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
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def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
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def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
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@ -1,7 +1,7 @@
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; RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
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; RUN: llc -march=sparc -O0 < %s | FileCheck %s -check-prefix=V8-UNOPT
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; RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
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; RUN: llc -mtriple=sparc64-unknown-linux < %s | FileCheck %s -check-prefix=SPARC64
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; V8-LABEL: test_neg:
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; V8: call get_double
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@ -16,6 +16,9 @@
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; V9-LABEL: test_neg:
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; V9: fnegd %f0, %f0
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; SPARC64-LABEL: test_neg:
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; SPARC64: fnegd %f0, %f0
|
||||
|
||||
define double @test_neg() {
|
||||
entry:
|
||||
%0 = tail call double @get_double()
|
||||
@ -35,6 +38,10 @@ entry:
|
||||
; V9-LABEL: test_abs:
|
||||
; V9: fabsd %f0, %f0
|
||||
|
||||
|
||||
; SPARC64-LABEL: test_abs:
|
||||
; SPARC64: fabsd %f0, %f0
|
||||
|
||||
define double @test_abs() {
|
||||
entry:
|
||||
%0 = tail call double @get_double()
|
||||
@ -56,6 +63,10 @@ declare double @llvm.fabs.f64(double) nounwind readonly
|
||||
; V9: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
|
||||
; V9: fmovd [[R]], %f0
|
||||
|
||||
; SPARC64-LABEL: test_v9_floatreg:
|
||||
; SPARC64: fsubd {{.+}}, {{.+}}, {{.+}}
|
||||
; SPARC64: faddd {{.+}}, {{.+}}, [[R:%f((3(2|4|6|8))|((4|5)(0|2|4|6|8))|(60|62))]]
|
||||
; SPARC64: fmovd [[R]], %f0
|
||||
|
||||
define double @test_v9_floatreg() {
|
||||
entry:
|
||||
@ -67,4 +78,172 @@ entry:
|
||||
ret double %3
|
||||
}
|
||||
|
||||
; V8-LABEL: test_xtos_stox
|
||||
; V8: call __floatdisf
|
||||
; V8: call __fixsfdi
|
||||
|
||||
; V9-LABEL: test_xtos_stox
|
||||
; V9: call __floatdisf
|
||||
; V9: call __fixsfdi
|
||||
|
||||
; SPARC64-LABEL: test_xtos_stox
|
||||
; SPARC64: fxtos
|
||||
; SPARC64: fstox
|
||||
|
||||
define void @test_xtos_stox(i64 %a, i64* %ptr0, float* %ptr1) {
|
||||
entry:
|
||||
%0 = sitofp i64 %a to float
|
||||
store float %0, float* %ptr1, align 8
|
||||
%1 = fptosi float %0 to i64
|
||||
store i64 %1, i64* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; V8-LABEL: test_itos_stoi
|
||||
; V8: fitos
|
||||
; V8: fstoi
|
||||
|
||||
; V9-LABEL: test_itos_stoi
|
||||
; V9: fitos
|
||||
; V9: fstoi
|
||||
|
||||
; SPARC64-LABEL: test_itos_stoi
|
||||
; SPARC64: fitos
|
||||
; SPARC64: fstoi
|
||||
|
||||
define void @test_itos_stoi(i32 %a, i32* %ptr0, float* %ptr1) {
|
||||
entry:
|
||||
%0 = sitofp i32 %a to float
|
||||
store float %0, float* %ptr1, align 8
|
||||
%1 = fptosi float %0 to i32
|
||||
store i32 %1, i32* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; V8-LABEL: test_xtod_dtox
|
||||
; V8: call __floatdidf
|
||||
; V8: call __fixdfdi
|
||||
|
||||
; V9-LABEL: test_xtod_dtox
|
||||
; V9: call __floatdidf
|
||||
; V9: call __fixdfdi
|
||||
|
||||
; SPARC64-LABEL: test_xtod_dtox
|
||||
; SPARC64: fxtod
|
||||
; SPARC64: fdtox
|
||||
|
||||
define void @test_xtod_dtox(i64 %a, i64* %ptr0, double* %ptr1) {
|
||||
entry:
|
||||
%0 = sitofp i64 %a to double
|
||||
store double %0, double* %ptr1, align 8
|
||||
%1 = fptosi double %0 to i64
|
||||
store i64 %1, i64* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; V8-LABEL: test_itod_dtoi
|
||||
; V8: fitod
|
||||
; V8: fdtoi
|
||||
|
||||
; V9-LABEL: test_itod_dtoi
|
||||
; V9: fitod
|
||||
; V9: fdtoi
|
||||
|
||||
; SPARC64-LABEL: test_itod_dtoi
|
||||
; SPARC64: fitod
|
||||
; SPARC64: fdtoi
|
||||
|
||||
define void @test_itod_dtoi(i32 %a, i32* %ptr0, double* %ptr1) {
|
||||
entry:
|
||||
%0 = sitofp i32 %a to double
|
||||
store double %0, double* %ptr1, align 8
|
||||
%1 = fptosi double %0 to i32
|
||||
store i32 %1, i32* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; V8-LABEL: test_uxtos_stoux
|
||||
; V8: call __floatundisf
|
||||
; V8: call __fixunssfdi
|
||||
|
||||
; V9-LABEL: test_uxtos_stoux
|
||||
; V9: call __floatundisf
|
||||
; V9: call __fixunssfdi
|
||||
|
||||
; SPARC64-LABEL: test_uxtos_stoux
|
||||
; SPARC64-NOT: call __floatundisf
|
||||
; SPARC64-NOT: call __fixunssfdi
|
||||
|
||||
define void @test_uxtos_stoux(i64 %a, i64* %ptr0, float* %ptr1) {
|
||||
entry:
|
||||
%0 = uitofp i64 %a to float
|
||||
store float %0, float* %ptr1, align 8
|
||||
%1 = fptoui float %0 to i64
|
||||
store i64 %1, i64* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; V8-LABEL: test_utos_stou
|
||||
; V8: fdtos
|
||||
; V8: fstoi
|
||||
|
||||
; V9-LABEL: test_utos_stou
|
||||
; V9: fdtos
|
||||
; V9: fstoi
|
||||
|
||||
; SPARC64-LABEL: test_utos_stou
|
||||
; SPARC64: fdtos
|
||||
; SPARC64: fstoi
|
||||
|
||||
define void @test_utos_stou(i32 %a, i32* %ptr0, float* %ptr1) {
|
||||
entry:
|
||||
%0 = uitofp i32 %a to float
|
||||
store float %0, float* %ptr1, align 8
|
||||
%1 = fptoui float %0 to i32
|
||||
store i32 %1, i32* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
; V8-LABEL: test_uxtod_dtoux
|
||||
; V8: call __floatundidf
|
||||
; V8: call __fixunsdfdi
|
||||
|
||||
; V9-LABEL: test_uxtod_dtoux
|
||||
; V9: call __floatundidf
|
||||
; V9: call __fixunsdfdi
|
||||
|
||||
; SPARC64-LABEL: test_uxtod_dtoux
|
||||
; SPARC64-NOT: call __floatundidf
|
||||
; SPARC64-NOT: call __floatunsdfdi
|
||||
|
||||
define void @test_uxtod_dtoux(i64 %a, i64* %ptr0, double* %ptr1) {
|
||||
entry:
|
||||
%0 = uitofp i64 %a to double
|
||||
store double %0, double* %ptr1, align 8
|
||||
%1 = fptoui double %0 to i64
|
||||
store i64 %1, i64* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; V8-LABEL: test_utod_dtou
|
||||
; V8-NOT: fitod
|
||||
; V8: fdtoi
|
||||
|
||||
; V9-LABEL: test_utod_dtou
|
||||
; V9-NOT: fitod
|
||||
; V9: fdtoi
|
||||
|
||||
; SPARC64-LABEL: test_utod_dtou
|
||||
; SPARC64-NOT: fitod
|
||||
; SPARC64: fdtoi
|
||||
|
||||
define void @test_utod_dtou(i32 %a, double %b, i32* %ptr0, double* %ptr1) {
|
||||
entry:
|
||||
%0 = uitofp i32 %a to double
|
||||
store double %0, double* %ptr1, align 8
|
||||
%1 = fptoui double %b to i32
|
||||
store i32 %1, i32* %ptr0, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
@ -180,3 +180,55 @@ entry:
|
||||
%4 = add i32 %2, %3
|
||||
ret i32 %4
|
||||
}
|
||||
|
||||
; HARD-LABEL: test_itoq_qtoi
|
||||
; HARD: call _Q_lltoq
|
||||
; HARD: call _Q_qtoll
|
||||
; HARD: fitoq
|
||||
; HARD: fqtoi
|
||||
|
||||
; SOFT-LABEL: test_itoq_qtoi
|
||||
; SOFT: call _Q_lltoq
|
||||
; SOFT: call _Q_qtoll
|
||||
; SOFT: call _Q_itoq
|
||||
; SOFT: call _Q_qtoi
|
||||
|
||||
define void @test_itoq_qtoi(i64 %a, i32 %b, i64* %ptr0, fp128* %ptr1) {
|
||||
entry:
|
||||
%0 = sitofp i64 %a to fp128
|
||||
store fp128 %0, fp128* %ptr1, align 8
|
||||
%1 = fptosi fp128 %0 to i64
|
||||
store i64 %1, i64* %ptr0, align 8
|
||||
%2 = sitofp i32 %b to fp128
|
||||
store fp128 %2, fp128* %ptr1, align 8
|
||||
%3 = fptosi fp128 %2 to i32
|
||||
%4 = bitcast i64* %ptr0 to i32*
|
||||
store i32 %3, i32* %4, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
; HARD-LABEL: test_utoq_qtou
|
||||
; HARD-DAG: call _Q_ulltoq
|
||||
; HARD-DAG: call _Q_qtoull
|
||||
; HARD-DAG: fdtoq
|
||||
; HARD-DAG: fqtoi
|
||||
|
||||
; SOFT-LABEL: test_utoq_qtou
|
||||
; SOFT-DAG: call _Q_ulltoq
|
||||
; SOFT-DAG: call _Q_qtoull
|
||||
; SOFT-DAG: call _Q_utoq
|
||||
; SOFT-DAG: call _Q_qtou
|
||||
|
||||
define void @test_utoq_qtou(i64 %a, i32 %b, i64* %ptr0, fp128* %ptr1) {
|
||||
entry:
|
||||
%0 = uitofp i64 %a to fp128
|
||||
store fp128 %0, fp128* %ptr1, align 8
|
||||
%1 = fptoui fp128 %0 to i64
|
||||
store i64 %1, i64* %ptr0, align 8
|
||||
%2 = uitofp i32 %b to fp128
|
||||
store fp128 %2, fp128* %ptr1, align 8
|
||||
%3 = fptoui fp128 %2 to i32
|
||||
%4 = bitcast i64* %ptr0 to i32*
|
||||
store i32 %3, i32* %4, align 8
|
||||
ret void
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user