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[mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is

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enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1)

This prevents the upper 32-bits of a double precision value from being moved to
the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure
that the code generated executes correctly regardless of the current FPU mode.

MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue
to use dmtc1.

Differential Revision: http://reviews.llvm.org/D4465


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sasa Stankovic
2014-07-14 09:40:29 +00:00
parent 5388e6f9b3
commit fce699d88a
8 changed files with 226 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
lib/Target/Mips/MipsSEFrameLowering.cpp
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@ -64,6 +64,8 @@ private:
bool expandCopy(MachineBasicBlock &MBB, Iter I);
bool expandCopyACC(MachineBasicBlock &MBB, Iter I, unsigned MFHiOpc,
unsigned MFLoOpc);
bool expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, bool FP64) const;
MachineFunction &MF;
MachineRegisterInfo &MRI;
@ -108,6 +110,14 @@ bool ExpandPseudo::expandInstr(MachineBasicBlock &MBB, Iter I) {
case Mips::STORE_ACC128:
expandStoreACC(MBB, I, Mips::PseudoMFHI64, Mips::PseudoMFLO64, 8);
break;
case Mips::BuildPairF64:
if (expandBuildPairF64(MBB, I, false))
MBB.erase(I);
return false;
case Mips::BuildPairF64_64:
if (expandBuildPairF64(MBB, I, true))
MBB.erase(I);
return false;
case TargetOpcode::COPY:
if (!expandCopy(MBB, I))
return false;
@ -258,6 +268,50 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
return true;
}
/// This method expands the same instruction that MipsSEInstrInfo::
/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is
/// not available. It is implemented here because frame indexes are
/// eliminated before MipsSEInstrInfo::expandBuildPairF64 is called.
bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
bool FP64) const {
// For fpxx and when mthc1 is not available, use:
// spill + reload via ldc1
//
// The case where dmtc1 is available doesn't need to be handled here
// because it never creates a BuildPairF64 node.
const TargetMachine &TM = MF.getTarget();
if (TM.getSubtarget<MipsSubtarget>().isABI_FPXX()
&& !TM.getSubtarget<MipsSubtarget>().hasMTHC1()) {
const MipsSEInstrInfo &TII =
*static_cast<const MipsSEInstrInfo*>(TM.getInstrInfo());
const MipsRegisterInfo &TRI =
*static_cast<const MipsRegisterInfo*>(TM.getRegisterInfo());
unsigned DstReg = I->getOperand(0).getReg();
unsigned LoReg = I->getOperand(1).getReg();
unsigned HiReg = I->getOperand(2).getReg();
// It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
// the cases where mthc1 is not available).
assert(!TM.getSubtarget<MipsSubtarget>().isFP64bit());
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
const TargetRegisterClass *RC2 = &Mips::AFGR64RegClass;
int FI = MF.getInfo<MipsFunctionInfo>()->getBuildPairF64_FI(RC2);
TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, &TRI,
0);
TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, &TRI,
4);
TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &TRI, 0);
return true;
}
return false;
}
MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
: MipsFrameLowering(STI, STI.stackAlignment()) {}