From fcfee179119d6d5872dde039046f7ecbf6eae776 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Mon, 5 Jan 2015 21:53:52 +0000 Subject: [PATCH] [PowerPC] Convert a README.txt entry into a better test We now produce the desired code as noted in the README.txt file (no spurious or). Remove the README entry and improve the regression test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225214 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/README.txt | 13 ------------- test/CodeGen/PowerPC/2007-03-24-cntlzd.ll | 8 +++++++- 2 files changed, 7 insertions(+), 14 deletions(-) diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt index 29238fd2a55..9571e4a0616 100644 --- a/lib/Target/PowerPC/README.txt +++ b/lib/Target/PowerPC/README.txt @@ -494,19 +494,6 @@ _bar: ===-------------------------------------------------------------------------=== -test/CodeGen/PowerPC/2007-03-24-cntlzd.ll compiles to: - -__ZNK4llvm5APInt17countLeadingZerosEv: - ld r2, 0(r3) - cntlzd r2, r2 - or r2, r2, r2 <<-- silly. - addi r3, r2, -64 - blr - -The dead or is a 'truncate' from 64- to 32-bits. - -===-------------------------------------------------------------------------=== - We generate horrible ppc code for this: #define N 2000000 diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll index 3620b0e6340..bbca76fd087 100644 --- a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll +++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 -mcpu=g5 | grep cntlzd +; RUN: llc < %s -march=ppc64 -mcpu=g5 | FileCheck %s define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind { %tmp19 = load i64* %t @@ -7,6 +7,12 @@ define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind { %tmp89 = add i32 %tmp23, -64 ; [#uses=1] %tmp90 = add i32 %tmp89, 0 ; [#uses=1] ret i32 %tmp90 + +; CHECK-LABEL: @_ZNK4llvm5APInt17countLeadingZerosEv +; CHECK: ld [[REG1:[0-9]+]], 0(3) +; CHECK-NEXT: cntlzd [[REG2:[0-9]+]], [[REG1]] +; CHECK-NEXT: addi 3, [[REG2]], -64 +; CHECK-NEXT: blr } declare i64 @llvm.ctlz.i64(i64, i1)