mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-05 13:09:10 +00:00
Add a version of ChooseRegOrImmed to handle numerical constants
introduced by InstrSelection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@3735 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve
parent
87fbcd99b4
commit
fd0ec80197
@ -312,6 +312,36 @@ Set3OperandsFromInstr(MachineInstr* minstr,
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(int64_t intValue,
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bool isSigned,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = isSigned? MachineOperand::MO_SignExtendedImmed
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: MachineOperand::MO_UnextendedImmed;
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getImmedValue = intValue;
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}
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else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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return opType;
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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@ -320,34 +350,16 @@ ChooseRegOrImmed(Value* val,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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// Check for the common case first: argument is not constant
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//
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// To use reg or immed, constant needs to be integer, bool, or a NULL pointer
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Constant *CPV = dyn_cast<Constant>(val);
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if (!CPV) return opType;
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if (CPV == NULL ||
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(! CPV->getType()->isIntegral() &&
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! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
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return MachineOperand::MO_VirtualRegister;
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if (ConstantBool *CPB = dyn_cast<ConstantBool>(CPV))
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{
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if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
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{
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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return MachineOperand::MO_MachineRegister;
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}
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getImmedValue = 1;
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return MachineOperand::MO_SignExtendedImmed;
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}
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// Otherwise it needs to be an integer or a NULL pointer
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if (! CPV->getType()->isInteger() &&
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! (isa<PointerType>(CPV->getType()) &&
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CPV->isNullValue()))
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return opType;
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// Now get the constant value and check if it fits in the IMMED field.
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// Take advantage of the fact that the max unsigned value will rarely
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// fit into any IMMED field and ignore that case (i.e., cast smaller
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@ -355,35 +367,22 @@ ChooseRegOrImmed(Value* val,
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//
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int64_t intValue;
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if (isa<PointerType>(CPV->getType()))
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{
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intValue = 0;
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}
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intValue = 0; // We checked above that it is NULL
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else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
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intValue = (int64_t) CB->getValue();
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else if (CPV->getType()->isSigned())
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{
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intValue = cast<ConstantSInt>(CPV)->getValue();
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}
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intValue = cast<ConstantSInt>(CPV)->getValue();
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else
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{
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assert(CPV->getType()->isUnsigned() && "Not pointer, bool, or integer?");
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uint64_t V = cast<ConstantUInt>(CPV)->getValue();
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if (V >= INT64_MAX) return opType;
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intValue = (int64_t)V;
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if (V >= INT64_MAX) return MachineOperand::MO_VirtualRegister;
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intValue = (int64_t) V;
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}
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if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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else if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = CPV->getType()->isSigned()
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? MachineOperand::MO_SignExtendedImmed
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: MachineOperand::MO_UnextendedImmed;
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getImmedValue = intValue;
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}
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return opType;
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return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
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opCode, target, canUseImmed,
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getMachineRegNum, getImmedValue);
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}
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@ -409,55 +408,91 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
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{
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vector<MachineInstr*> loadConstVec;
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const MachineInstrDescriptor& instrDesc =
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target.getInstrInfo().getDescriptor(minstr->getOpCode());
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MachineOpCode opCode = minstr->getOpCode();
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const MachineInstrInfo& instrInfo = target.getInstrInfo();
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const MachineInstrDescriptor& instrDesc = instrInfo.getDescriptor(opCode);
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int immedPos = instrInfo.getImmedConstantPos(opCode);
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Function *F = vmInstr->getParent()->getParent();
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for (unsigned op=0; op < minstr->getNumOperands(); op++)
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{
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const MachineOperand& mop = minstr->getOperand(op);
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// skip the result position (for efficiency below) and any other
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// positions already marked as not a virtual register
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if (instrDesc.resultPos == (int) op ||
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mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
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mop.getVRegValue() == NULL)
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{
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continue;
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}
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Value* opValue = mop.getVRegValue();
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// Skip the result position, preallocated machine registers, or operands
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// that cannot be constants (CC regs or PC-relative displacements)
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if (instrDesc.resultPos == (int) op ||
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mop.getOperandType() == MachineOperand::MO_MachineRegister ||
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mop.getOperandType() == MachineOperand::MO_CCRegister ||
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mop.getOperandType() == MachineOperand::MO_PCRelativeDisp)
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continue;
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bool constantThatMustBeLoaded = false;
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if (Constant *opConst = dyn_cast<Constant>(opValue))
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unsigned int machineRegNum = 0;
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int64_t immedValue = 0;
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Value* opValue = NULL;
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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// Operand may be a virtual register or a compile-time constant
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if (mop.getOperandType() == MachineOperand::MO_VirtualRegister)
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{
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unsigned int machineRegNum;
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int64_t immedValue;
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MachineOperand::MachineOperandType opType =
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ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
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(target.getInstrInfo().getImmedConstantPos(minstr->getOpCode()) == (int) op),
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machineRegNum, immedValue);
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if (opType == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperandReg(op, machineRegNum);
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else if (opType == MachineOperand::MO_VirtualRegister)
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constantThatMustBeLoaded = true; // load is generated below
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else
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minstr->SetMachineOperandConst(op, opType, immedValue);
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assert(mop.getVRegValue() != NULL);
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opValue = mop.getVRegValue();
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if (Constant *opConst = dyn_cast<Constant>(opValue))
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{
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opType = ChooseRegOrImmed(opConst, opCode, target,
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(immedPos == (int)op), machineRegNum, immedValue);
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if (opType == MachineOperand::MO_VirtualRegister)
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constantThatMustBeLoaded = true;
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}
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}
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if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
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{ // opValue is a constant that must be explicitly loaded into a reg.
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TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue,vmInstr,
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loadConstVec,
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target);
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else
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{
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assert(mop.getOperandType() == MachineOperand::MO_SignExtendedImmed ||
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mop.getOperandType() == MachineOperand::MO_UnextendedImmed);
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bool isSigned = (mop.getOperandType() ==
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MachineOperand::MO_SignExtendedImmed);
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// Bit-selection flags indicate an instruction that is extracting
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// bits from its operand so ignore this even if it is a big constant.
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if (mop.opHiBits32() || mop.opLoBits32() ||
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mop.opHiBits64() || mop.opLoBits64())
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continue;
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opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
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opCode, target, (immedPos == (int)op),
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machineRegNum, immedValue);
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if (opType == mop.getOperandType())
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continue; // no change: this is the most common case
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if (opType == MachineOperand::MO_VirtualRegister)
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{
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constantThatMustBeLoaded = true;
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opValue = isSigned
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? ConstantSInt::get(Type::LongTy, immedValue)
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: ConstantUInt::get(Type::ULongTy, (uint64_t) immedValue);
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}
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}
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if (opType == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperandReg(op, machineRegNum);
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else if (opType == MachineOperand::MO_SignExtendedImmed ||
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opType == MachineOperand::MO_UnextendedImmed)
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minstr->SetMachineOperandConst(op, opType, immedValue);
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else if (constantThatMustBeLoaded ||
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(opValue && isa<GlobalValue>(opValue)))
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{ // opValue is a constant that must be explicitly loaded into a reg
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assert(opValue);
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TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
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loadConstVec, target);
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minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
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tmpReg);
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}
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}
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//
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// Also, check for implicit operands used by the machine instruction
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// (no need to check those defined since they cannot be constants).
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// These include:
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@ -468,7 +503,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
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// have no immediate fields, so the constant always needs to be loaded
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// into a register.
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//
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bool isCall = target.getInstrInfo().isCall(minstr->getOpCode());
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bool isCall = instrInfo.isCall(opCode);
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unsigned lastCallArgNum = 0; // unused if not a call
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CallArgsDescriptor* argDesc = NULL; // unused if not a call
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if (isCall)
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@ -312,6 +312,36 @@ Set3OperandsFromInstr(MachineInstr* minstr,
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(int64_t intValue,
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bool isSigned,
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MachineOpCode opCode,
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const TargetMachine& target,
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bool canUseImmed,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType=MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = isSigned? MachineOperand::MO_SignExtendedImmed
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: MachineOperand::MO_UnextendedImmed;
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getImmedValue = intValue;
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}
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else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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return opType;
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}
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MachineOperand::MachineOperandType
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ChooseRegOrImmed(Value* val,
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MachineOpCode opCode,
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@ -320,34 +350,16 @@ ChooseRegOrImmed(Value* val,
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unsigned int& getMachineRegNum,
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int64_t& getImmedValue)
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{
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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getMachineRegNum = 0;
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getImmedValue = 0;
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// Check for the common case first: argument is not constant
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//
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// To use reg or immed, constant needs to be integer, bool, or a NULL pointer
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Constant *CPV = dyn_cast<Constant>(val);
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if (!CPV) return opType;
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if (CPV == NULL ||
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(! CPV->getType()->isIntegral() &&
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! (isa<PointerType>(CPV->getType()) && CPV->isNullValue())))
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return MachineOperand::MO_VirtualRegister;
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if (ConstantBool *CPB = dyn_cast<ConstantBool>(CPV))
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{
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if (!CPB->getValue() && target.getRegInfo().getZeroRegNum() >= 0)
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{
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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return MachineOperand::MO_MachineRegister;
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}
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getImmedValue = 1;
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return MachineOperand::MO_SignExtendedImmed;
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}
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// Otherwise it needs to be an integer or a NULL pointer
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if (! CPV->getType()->isInteger() &&
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! (isa<PointerType>(CPV->getType()) &&
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CPV->isNullValue()))
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return opType;
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// Now get the constant value and check if it fits in the IMMED field.
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// Take advantage of the fact that the max unsigned value will rarely
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// fit into any IMMED field and ignore that case (i.e., cast smaller
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@ -355,35 +367,22 @@ ChooseRegOrImmed(Value* val,
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//
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int64_t intValue;
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if (isa<PointerType>(CPV->getType()))
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{
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intValue = 0;
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}
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intValue = 0; // We checked above that it is NULL
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else if (ConstantBool* CB = dyn_cast<ConstantBool>(CPV))
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intValue = (int64_t) CB->getValue();
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else if (CPV->getType()->isSigned())
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{
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intValue = cast<ConstantSInt>(CPV)->getValue();
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}
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intValue = cast<ConstantSInt>(CPV)->getValue();
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else
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{
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assert(CPV->getType()->isUnsigned() && "Not pointer, bool, or integer?");
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uint64_t V = cast<ConstantUInt>(CPV)->getValue();
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if (V >= INT64_MAX) return opType;
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intValue = (int64_t)V;
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if (V >= INT64_MAX) return MachineOperand::MO_VirtualRegister;
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intValue = (int64_t) V;
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}
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if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0)
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{
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opType = MachineOperand::MO_MachineRegister;
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getMachineRegNum = target.getRegInfo().getZeroRegNum();
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}
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else if (canUseImmed &&
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target.getInstrInfo().constantFitsInImmedField(opCode, intValue))
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{
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opType = CPV->getType()->isSigned()
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? MachineOperand::MO_SignExtendedImmed
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: MachineOperand::MO_UnextendedImmed;
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getImmedValue = intValue;
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}
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return opType;
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return ChooseRegOrImmed(intValue, CPV->getType()->isSigned(),
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opCode, target, canUseImmed,
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getMachineRegNum, getImmedValue);
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}
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@ -409,55 +408,91 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
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{
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vector<MachineInstr*> loadConstVec;
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const MachineInstrDescriptor& instrDesc =
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target.getInstrInfo().getDescriptor(minstr->getOpCode());
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MachineOpCode opCode = minstr->getOpCode();
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const MachineInstrInfo& instrInfo = target.getInstrInfo();
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const MachineInstrDescriptor& instrDesc = instrInfo.getDescriptor(opCode);
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int immedPos = instrInfo.getImmedConstantPos(opCode);
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Function *F = vmInstr->getParent()->getParent();
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for (unsigned op=0; op < minstr->getNumOperands(); op++)
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{
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const MachineOperand& mop = minstr->getOperand(op);
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// skip the result position (for efficiency below) and any other
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// positions already marked as not a virtual register
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if (instrDesc.resultPos == (int) op ||
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mop.getOperandType() != MachineOperand::MO_VirtualRegister ||
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mop.getVRegValue() == NULL)
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{
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continue;
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}
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Value* opValue = mop.getVRegValue();
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// Skip the result position, preallocated machine registers, or operands
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// that cannot be constants (CC regs or PC-relative displacements)
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if (instrDesc.resultPos == (int) op ||
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mop.getOperandType() == MachineOperand::MO_MachineRegister ||
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mop.getOperandType() == MachineOperand::MO_CCRegister ||
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mop.getOperandType() == MachineOperand::MO_PCRelativeDisp)
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continue;
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bool constantThatMustBeLoaded = false;
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if (Constant *opConst = dyn_cast<Constant>(opValue))
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unsigned int machineRegNum = 0;
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int64_t immedValue = 0;
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Value* opValue = NULL;
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MachineOperand::MachineOperandType opType =
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MachineOperand::MO_VirtualRegister;
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// Operand may be a virtual register or a compile-time constant
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if (mop.getOperandType() == MachineOperand::MO_VirtualRegister)
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{
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unsigned int machineRegNum;
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int64_t immedValue;
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MachineOperand::MachineOperandType opType =
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ChooseRegOrImmed(opValue, minstr->getOpCode(), target,
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(target.getInstrInfo().getImmedConstantPos(minstr->getOpCode()) == (int) op),
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machineRegNum, immedValue);
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if (opType == MachineOperand::MO_MachineRegister)
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minstr->SetMachineOperandReg(op, machineRegNum);
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else if (opType == MachineOperand::MO_VirtualRegister)
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constantThatMustBeLoaded = true; // load is generated below
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else
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minstr->SetMachineOperandConst(op, opType, immedValue);
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assert(mop.getVRegValue() != NULL);
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opValue = mop.getVRegValue();
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if (Constant *opConst = dyn_cast<Constant>(opValue))
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{
|
||||
opType = ChooseRegOrImmed(opConst, opCode, target,
|
||||
(immedPos == (int)op), machineRegNum, immedValue);
|
||||
if (opType == MachineOperand::MO_VirtualRegister)
|
||||
constantThatMustBeLoaded = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (constantThatMustBeLoaded || isa<GlobalValue>(opValue))
|
||||
{ // opValue is a constant that must be explicitly loaded into a reg.
|
||||
TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue,vmInstr,
|
||||
loadConstVec,
|
||||
target);
|
||||
else
|
||||
{
|
||||
assert(mop.getOperandType() == MachineOperand::MO_SignExtendedImmed ||
|
||||
mop.getOperandType() == MachineOperand::MO_UnextendedImmed);
|
||||
|
||||
bool isSigned = (mop.getOperandType() ==
|
||||
MachineOperand::MO_SignExtendedImmed);
|
||||
|
||||
// Bit-selection flags indicate an instruction that is extracting
|
||||
// bits from its operand so ignore this even if it is a big constant.
|
||||
if (mop.opHiBits32() || mop.opLoBits32() ||
|
||||
mop.opHiBits64() || mop.opLoBits64())
|
||||
continue;
|
||||
|
||||
opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
|
||||
opCode, target, (immedPos == (int)op),
|
||||
machineRegNum, immedValue);
|
||||
|
||||
if (opType == mop.getOperandType())
|
||||
continue; // no change: this is the most common case
|
||||
|
||||
if (opType == MachineOperand::MO_VirtualRegister)
|
||||
{
|
||||
constantThatMustBeLoaded = true;
|
||||
opValue = isSigned
|
||||
? ConstantSInt::get(Type::LongTy, immedValue)
|
||||
: ConstantUInt::get(Type::ULongTy, (uint64_t) immedValue);
|
||||
}
|
||||
}
|
||||
|
||||
if (opType == MachineOperand::MO_MachineRegister)
|
||||
minstr->SetMachineOperandReg(op, machineRegNum);
|
||||
else if (opType == MachineOperand::MO_SignExtendedImmed ||
|
||||
opType == MachineOperand::MO_UnextendedImmed)
|
||||
minstr->SetMachineOperandConst(op, opType, immedValue);
|
||||
else if (constantThatMustBeLoaded ||
|
||||
(opValue && isa<GlobalValue>(opValue)))
|
||||
{ // opValue is a constant that must be explicitly loaded into a reg
|
||||
assert(opValue);
|
||||
TmpInstruction* tmpReg = InsertCodeToLoadConstant(F, opValue, vmInstr,
|
||||
loadConstVec, target);
|
||||
minstr->SetMachineOperandVal(op, MachineOperand::MO_VirtualRegister,
|
||||
tmpReg);
|
||||
}
|
||||
}
|
||||
|
||||
//
|
||||
// Also, check for implicit operands used by the machine instruction
|
||||
// (no need to check those defined since they cannot be constants).
|
||||
// These include:
|
||||
@ -468,7 +503,7 @@ FixConstantOperandsForInstr(Instruction* vmInstr,
|
||||
// have no immediate fields, so the constant always needs to be loaded
|
||||
// into a register.
|
||||
//
|
||||
bool isCall = target.getInstrInfo().isCall(minstr->getOpCode());
|
||||
bool isCall = instrInfo.isCall(opCode);
|
||||
unsigned lastCallArgNum = 0; // unused if not a call
|
||||
CallArgsDescriptor* argDesc = NULL; // unused if not a call
|
||||
if (isCall)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user