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Add MachineMemOperands to instructions generated in storeRegToStackSlot or

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loadRegFromStackSlot. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147235 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-12-24 03:11:18 +00:00
parent 9dfd4399a9
commit fd1d9250b2
1 changed files with 16 additions and 2 deletions
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18
lib/Target/Mips/MipsInstrInfo.cpp
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@ -168,6 +168,16 @@ copyPhysReg(MachineBasicBlock &MBB,
MIB.addReg(SrcReg, getKillRegState(KillSrc)); MIB.addReg(SrcReg, getKillRegState(KillSrc));
} }
static MachineMemOperand* GetMemOperand(MachineBasicBlock &MBB, int FI,
unsigned Flag) {
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = *MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI);
return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), Flag,
MFI.getObjectSize(FI), Align);
}
void MipsInstrInfo:: void MipsInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI, unsigned SrcReg, bool isKill, int FI,
@ -175,6 +185,8 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
unsigned Opc = 0; unsigned Opc = 0;
if (RC == Mips::CPURegsRegisterClass) if (RC == Mips::CPURegsRegisterClass)
@ -190,7 +202,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
assert(Opc && "Register class not handled!"); assert(Opc && "Register class not handled!");
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI).addImm(0); .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
} }
void MipsInstrInfo:: void MipsInstrInfo::
@ -201,6 +213,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
{ {
DebugLoc DL; DebugLoc DL;
if (I != MBB.end()) DL = I->getDebugLoc(); if (I != MBB.end()) DL = I->getDebugLoc();
MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
unsigned Opc = 0; unsigned Opc = 0;
if (RC == Mips::CPURegsRegisterClass) if (RC == Mips::CPURegsRegisterClass)
@ -215,7 +228,8 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164; Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
assert(Opc && "Register class not handled!"); assert(Opc && "Register class not handled!");
BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0); BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
.addMemOperand(MMO);
} }
MachineInstr* MachineInstr*