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[mips] Add patterns for DSP indexed load instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-03-30 02:14:45 +00:00
parent 175f0fd99a
commit fd2cd0db97
3 changed files with 73 additions and 13 deletions
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11
lib/Target/Mips/MipsDSPInstrInfo.td
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@ -1258,3 +1258,14 @@ def : EXTR_W_TY1_R2_Pat<MipsEXTR_S_H, EXTRV_S_H>;
let AddedComplexity = 20 in
def : DSPPat<(i32 (ExtractLOHI ACRegsDSP:$ac, imm:$lohi_idx)),
(EXTRACT_SUBREG ACRegsDSP:$ac, imm:$lohi_idx)>;
// Indexed load patterns.
class IndexedLoadPat<SDPatternOperator LoadNode, Instruction Instr> :
DSPPat<(i32 (LoadNode (add i32:$base, i32:$index))),
(Instr i32:$base, i32:$index)>;
let AddedComplexity = 20 in {
def : IndexedLoadPat<zextloadi8, LBUX>;
def : IndexedLoadPat<sextloadi16, LHX>;
def : IndexedLoadPat<load, LWX>;
}

44
lib/Target/Mips/MipsInstrInfo.td
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@ -440,35 +440,39 @@ class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
// Memory Load/Store
class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
Operand MemOpnd> :
Operand MemOpnd, ComplexPattern Addr> :
InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
[(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem";
let canFoldAsLoad = 1;
let mayLoad = 1;
}
class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
Operand MemOpnd> :
Operand MemOpnd, ComplexPattern Addr> :
InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
[(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
[(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI> {
let DecoderMethod = "DecodeMem";
let mayStore = 1;
}
multiclass LoadM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
SDPatternOperator OpNode = null_frag,
ComplexPattern Addr = addr> {
def NAME : Load<opstr, OpNode, RC, mem, Addr>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Load<opstr, OpNode, RC, mem64, Addr>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
}
multiclass StoreM<string opstr, RegisterClass RC,
SDPatternOperator OpNode = null_frag> {
def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
SDPatternOperator OpNode = null_frag,
ComplexPattern Addr = addr> {
def NAME : Store<opstr, OpNode, RC, mem, Addr>, Requires<[NotN64, HasStdEnc]>;
def _P8 : Store<opstr, OpNode, RC, mem64, Addr>,
Requires<[IsN64, HasStdEnc]> {
let DecoderNamespace = "Mips64";
let isCodeGenOnly = 1;
}
@ -891,10 +895,10 @@ let Predicates = [HasMips32r2, HasStdEnc] in {
/// Load and Store Instructions
/// aligned
defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, LW_FM<0x24>;
defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, LW_FM<0x21>;
defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
defm LW : LoadM<"lw", CPURegs, load, addrDefault>, LW_FM<0x23>;
defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
@ -1290,6 +1294,20 @@ def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
(EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
// Load halfword/word patterns.
let AddedComplexity = 40 in {
let Predicates = [NotN64, HasStdEnc] in {
def : LoadRegImmPat<LBu, i32, zextloadi8>;
def : LoadRegImmPat<LH, i32, sextloadi16>;
def : LoadRegImmPat<LW, i32, load>;
}
let Predicates = [IsN64, HasStdEnc] in {
def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
def : LoadRegImmPat<LW_P8, i32, load>;
}
}
//===----------------------------------------------------------------------===//
// Floating Point Support
//===----------------------------------------------------------------------===//

31
test/CodeGen/Mips/dsp-patterns.ll Normal file
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@ -0,0 +1,31 @@
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
; CHECK: test_lbux:
; CHECK: lbux ${{[0-9]+}}
define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
entry:
%add.ptr = getelementptr inbounds i8* %b, i32 %i
%0 = load i8* %add.ptr, align 1
ret i8 %0
}
; CHECK: test_lhx:
; CHECK: lhx ${{[0-9]+}}
define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
entry:
%add.ptr = getelementptr inbounds i16* %b, i32 %i
%0 = load i16* %add.ptr, align 2
ret i16 %0
}
; CHECK: test_lwx:
; CHECK: lwx ${{[0-9]+}}
define i32 @test_lwx(i32* nocapture %b, i32 %i) {
entry:
%add.ptr = getelementptr inbounds i32* %b, i32 %i
%0 = load i32* %add.ptr, align 4
ret i32 %0
}