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[ARM64] Improve diagnostics for Cn operands in SYS instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208902 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2108,80 +2108,31 @@ int ARM64AsmParser::tryMatchVectorRegister(StringRef &Kind, bool expected) {
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return -1;
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return -1;
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}
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}
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static int MatchSysCRName(StringRef Name) {
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// Use the same layout as the tablegen'erated register name matcher. Ugly,
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// but efficient.
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switch (Name.size()) {
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default:
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break;
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case 2:
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if (Name[0] != 'c' && Name[0] != 'C')
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return -1;
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switch (Name[1]) {
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default:
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return -1;
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case '0':
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return 0;
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case '1':
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return 1;
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case '2':
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return 2;
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case '3':
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return 3;
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case '4':
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return 4;
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case '5':
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return 5;
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case '6':
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return 6;
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case '7':
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return 7;
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case '8':
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return 8;
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case '9':
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return 9;
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}
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break;
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case 3:
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if ((Name[0] != 'c' && Name[0] != 'C') || Name[1] != '1')
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return -1;
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switch (Name[2]) {
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default:
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return -1;
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case '0':
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return 10;
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case '1':
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return 11;
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case '2':
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return 12;
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case '3':
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return 13;
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case '4':
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return 14;
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case '5':
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return 15;
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}
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break;
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}
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llvm_unreachable("Unhandled SysCR operand string!");
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return -1;
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}
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/// tryParseSysCROperand - Try to parse a system instruction CR operand name.
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/// tryParseSysCROperand - Try to parse a system instruction CR operand name.
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ARM64AsmParser::OperandMatchResultTy
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ARM64AsmParser::OperandMatchResultTy
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ARM64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
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ARM64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
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SMLoc S = getLoc();
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SMLoc S = getLoc();
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const AsmToken &Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return MatchOperand_NoMatch;
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int Num = MatchSysCRName(Tok.getString());
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if (Parser.getTok().isNot(AsmToken::Identifier)) {
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if (Num == -1)
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Error(S, "Expected cN operand where 0 <= N <= 15");
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return MatchOperand_NoMatch;
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return MatchOperand_ParseFail;
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}
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StringRef Tok = Parser.getTok().getIdentifier();
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if (Tok[0] != 'c' && Tok[0] != 'C') {
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Error(S, "Expected cN operand where 0 <= N <= 15");
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return MatchOperand_ParseFail;
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}
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uint32_t CRNum;
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bool BadNum = Tok.drop_front().getAsInteger(10, CRNum);
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if (BadNum || CRNum > 15) {
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Error(S, "Expected cN operand where 0 <= N <= 15");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat identifier token.
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Parser.Lex(); // Eat identifier token.
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Operands.push_back(ARM64Operand::CreateSysCR(Num, S, getLoc(), getContext()));
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Operands.push_back(ARM64Operand::CreateSysCR(CRNum, S, getLoc(), getContext()));
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return MatchOperand_Success;
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return MatchOperand_Success;
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}
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}
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@ -3471,8 +3422,12 @@ bool ARM64AsmParser::ParseInstruction(ParseInstructionInfo &Info,
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StringRef Head = Name.slice(Start, Next);
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StringRef Head = Name.slice(Start, Next);
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// IC, DC, AT, and TLBI instructions are aliases for the SYS instruction.
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// IC, DC, AT, and TLBI instructions are aliases for the SYS instruction.
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if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi")
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if (Head == "ic" || Head == "dc" || Head == "at" || Head == "tlbi") {
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return parseSysAlias(Head, NameLoc, Operands);
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bool IsError = parseSysAlias(Head, NameLoc, Operands);
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if (IsError && getLexer().isNot(AsmToken::EndOfStatement))
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Parser.eatToEndOfStatement();
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return IsError;
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}
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Operands.push_back(
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Operands.push_back(
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ARM64Operand::CreateToken(Head, false, NameLoc, getContext()));
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ARM64Operand::CreateToken(Head, false, NameLoc, getContext()));
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@ -52,7 +52,7 @@ foo:
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; Check for error on invalid 'C' operand value.
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; Check for error on invalid 'C' operand value.
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sys #2, c16, c5, #7
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sys #2, c16, c5, #7
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; CHECK-ERRORS: invalid operand for instruction
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; CHECK-ERRORS: error: Expected cN operand where 0 <= N <= 15
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;-----------------------------------------------------------------------------
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;-----------------------------------------------------------------------------
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; MSR/MRS instructions
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; MSR/MRS instructions
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