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[CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239553 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -405,7 +405,7 @@ public:
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/// merging needs to be disabled.
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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DebugLoc DL) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::InsertBranch!");
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}
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@@ -530,7 +530,7 @@ public:
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/// @param TrueCycles Latency from TrueReg to select output.
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/// @param FalseCycles Latency from FalseReg to select output.
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virtual bool canInsertSelect(const MachineBasicBlock &MBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg,
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int &CondCycles,
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int &TrueCycles, int &FalseCycles) const {
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@@ -554,8 +554,7 @@ public:
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/// @param FalseReg Virtual register to copy when Cons is false.
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virtual void insertSelect(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DstReg,
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const SmallVectorImpl<MachineOperand> &Cond,
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unsigned DstReg, ArrayRef<MachineOperand> Cond,
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unsigned TrueReg, unsigned FalseReg) const {
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llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!");
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}
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@@ -878,13 +877,13 @@ public:
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/// It returns true if the operation was successful.
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Pred) const;
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ArrayRef<MachineOperand> Pred) const;
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/// Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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virtual
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const {
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bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
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ArrayRef<MachineOperand> Pred2) const {
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return false;
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}
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