mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-25 00:33:15 +00:00
Clang-format over X86AsmInstrumentation.* with LLVM style.
r216536 mistakenly used -style=Google instead of LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216543 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evgeniy Stepanov
parent
ccce7032ae
commit
fda6b888a9
@ -42,7 +42,7 @@ std::string FuncName(unsigned AccessSize, bool IsWrite) {
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}
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class X86AddressSanitizer : public X86AsmInstrumentation {
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public:
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public:
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X86AddressSanitizer(const MCSubtargetInfo &STI)
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: X86AsmInstrumentation(STI), RepPrefix(false) {}
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virtual ~X86AddressSanitizer() {}
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@ -54,12 +54,14 @@ class X86AddressSanitizer : public X86AsmInstrumentation {
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const MCInstrInfo &MII,
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MCStreamer &Out) override {
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InstrumentMOVS(Inst, Operands, Ctx, MII, Out);
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if (RepPrefix) EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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if (RepPrefix)
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EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX));
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InstrumentMOV(Inst, Operands, Ctx, MII, Out);
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RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX);
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if (!RepPrefix) EmitInstruction(Out, Inst);
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if (!RepPrefix)
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EmitInstruction(Out, Inst);
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}
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// Should be implemented differently in x86_32 and x86_64 subclasses.
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@ -85,7 +87,7 @@ class X86AddressSanitizer : public X86AsmInstrumentation {
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void EmitLabel(MCStreamer &Out, MCSymbol *Label) { Out.EmitLabel(Label); }
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protected:
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protected:
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// True when previous instruction was actually REP prefix.
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bool RepPrefix;
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};
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@ -161,20 +163,20 @@ void X86AddressSanitizer::InstrumentMOVS(const MCInst &Inst,
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOVSB:
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AccessSize = 1;
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break;
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case X86::MOVSW:
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AccessSize = 2;
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break;
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case X86::MOVSL:
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AccessSize = 4;
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break;
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case X86::MOVSQ:
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AccessSize = 8;
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break;
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default:
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return;
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case X86::MOVSB:
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AccessSize = 1;
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break;
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case X86::MOVSW:
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AccessSize = 2;
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break;
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case X86::MOVSL:
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AccessSize = 4;
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break;
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case X86::MOVSQ:
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AccessSize = 8;
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break;
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default:
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return;
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}
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InstrumentMOVSImpl(AccessSize, Ctx, Out);
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@ -188,46 +190,47 @@ void X86AddressSanitizer::InstrumentMOV(const MCInst &Inst,
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unsigned AccessSize = 0;
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switch (Inst.getOpcode()) {
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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case X86::MOV8mi:
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case X86::MOV8mr:
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case X86::MOV8rm:
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AccessSize = 1;
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break;
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case X86::MOV16mi:
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case X86::MOV16mr:
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case X86::MOV16rm:
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AccessSize = 2;
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break;
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case X86::MOV32mi:
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case X86::MOV32mr:
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case X86::MOV32rm:
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AccessSize = 4;
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break;
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case X86::MOV64mi32:
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case X86::MOV64mr:
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case X86::MOV64rm:
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AccessSize = 8;
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break;
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case X86::MOVAPDmr:
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case X86::MOVAPSmr:
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case X86::MOVAPDrm:
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case X86::MOVAPSrm:
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AccessSize = 16;
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break;
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default:
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return;
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}
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const bool IsWrite = MII.get(Inst.getOpcode()).mayStore();
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for (unsigned Ix = 0; Ix < Operands.size(); ++Ix) {
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assert(Operands[Ix]);
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MCParsedAsmOperand &Op = *Operands[Ix];
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if (Op.isMem()) InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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if (Op.isMem())
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InstrumentMemOperand(Op, AccessSize, IsWrite, Ctx, Out);
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}
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}
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class X86AddressSanitizer32 : public X86AddressSanitizer {
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public:
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public:
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static const long kShadowOffset = 0x20000000;
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X86AddressSanitizer32(const MCSubtargetInfo &STI)
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@ -245,7 +248,7 @@ class X86AddressSanitizer32 : public X86AddressSanitizer {
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) override;
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private:
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private:
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void EmitCallAsanReport(MCContext &Ctx, MCStreamer &Out, unsigned AccessSize,
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bool IsWrite, unsigned AddressReg) {
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EmitInstruction(Out, MCInstBuilder(X86::CLD));
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@ -313,29 +316,29 @@ void X86AddressSanitizer32::InstrumentMemOperandSmallImpl(X86Operand &Op,
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MCInstBuilder(X86::AND32ri).addReg(X86::EDX).addReg(X86::EDX).addImm(7));
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switch (AccessSize) {
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EDX));
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::EDX));
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::EDX)
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.addReg(X86::EDX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::EDX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::EDX)
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.addReg(X86::EDX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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EmitInstruction(
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@ -377,15 +380,15 @@ void X86AddressSanitizer32::InstrumentMemOperandLargeImpl(X86Operand &Op,
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{
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MCInst Inst;
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switch (AccessSize) {
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case 8:
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Inst.setOpcode(X86::CMP8mi);
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break;
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case 16:
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Inst.setOpcode(X86::CMP16mi);
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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case 8:
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Inst.setOpcode(X86::CMP8mi);
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break;
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case 16:
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Inst.setOpcode(X86::CMP16mi);
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
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std::unique_ptr<X86Operand> Op(
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@ -427,7 +430,7 @@ void X86AddressSanitizer32::InstrumentMOVSImpl(unsigned AccessSize,
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}
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class X86AddressSanitizer64 : public X86AddressSanitizer {
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public:
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public:
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static const long kShadowOffset = 0x7fff8000;
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X86AddressSanitizer64(const MCSubtargetInfo &STI)
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@ -445,7 +448,7 @@ class X86AddressSanitizer64 : public X86AddressSanitizer {
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virtual void InstrumentMOVSImpl(unsigned AccessSize, MCContext &Ctx,
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MCStreamer &Out) override;
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private:
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private:
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void EmitAdjustRSP(MCContext &Ctx, MCStreamer &Out, long Offset) {
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MCInst Inst;
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Inst.setOpcode(X86::LEA64r);
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@ -522,29 +525,29 @@ void X86AddressSanitizer64::InstrumentMemOperandSmallImpl(X86Operand &Op,
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MCInstBuilder(X86::AND32ri).addReg(X86::ECX).addReg(X86::ECX).addImm(7));
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switch (AccessSize) {
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::ECX));
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case 1:
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break;
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case 2: {
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MCInst Inst;
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Inst.setOpcode(X86::LEA32r);
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Inst.addOperand(MCOperand::CreateReg(X86::ECX));
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::ECX)
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.addReg(X86::ECX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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const MCExpr *Disp = MCConstantExpr::Create(1, Ctx);
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std::unique_ptr<X86Operand> Op(
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X86Operand::CreateMem(0, Disp, X86::ECX, 0, 1, SMLoc(), SMLoc()));
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Op->addMemOperands(Inst, 5);
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EmitInstruction(Out, Inst);
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break;
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}
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case 4:
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EmitInstruction(Out, MCInstBuilder(X86::ADD32ri8)
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.addReg(X86::ECX)
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.addReg(X86::ECX)
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.addImm(3));
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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EmitInstruction(
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@ -585,15 +588,15 @@ void X86AddressSanitizer64::InstrumentMemOperandLargeImpl(X86Operand &Op,
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{
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MCInst Inst;
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switch (AccessSize) {
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case 8:
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Inst.setOpcode(X86::CMP8mi);
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break;
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case 16:
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Inst.setOpcode(X86::CMP16mi);
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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case 8:
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Inst.setOpcode(X86::CMP8mi);
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break;
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case 16:
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Inst.setOpcode(X86::CMP16mi);
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break;
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default:
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assert(false && "Incorrect access size");
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break;
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}
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const MCExpr *Disp = MCConstantExpr::Create(kShadowOffset, Ctx);
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std::unique_ptr<X86Operand> Op(
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@ -635,7 +638,7 @@ void X86AddressSanitizer64::InstrumentMOVSImpl(unsigned AccessSize,
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EmitInstruction(Out, MCInstBuilder(X86::POPF64));
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}
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} // End anonymous namespace
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} // End anonymous namespace
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X86AsmInstrumentation::X86AsmInstrumentation(const MCSubtargetInfo &STI)
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: STI(STI) {}
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@ -653,9 +656,9 @@ void X86AsmInstrumentation::EmitInstruction(MCStreamer &Out,
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Out.EmitInstruction(Inst, STI);
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}
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X86AsmInstrumentation *CreateX86AsmInstrumentation(
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const MCTargetOptions &MCOptions, const MCContext &Ctx,
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const MCSubtargetInfo &STI) {
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X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI) {
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Triple T(STI.getTargetTriple());
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const bool hasCompilerRTSupport = T.isOSLinux();
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if (ClAsanInstrumentAssembly && hasCompilerRTSupport &&
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@ -668,4 +671,4 @@ X86AsmInstrumentation *CreateX86AsmInstrumentation(
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return new X86AsmInstrumentation(STI);
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}
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} // End llvm namespace
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} // End llvm namespace
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@ -26,12 +26,12 @@ class MCTargetOptions;
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class X86AsmInstrumentation;
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X86AsmInstrumentation *CreateX86AsmInstrumentation(
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const MCTargetOptions &MCOptions, const MCContext &Ctx,
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const MCSubtargetInfo &STI);
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X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI);
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class X86AsmInstrumentation {
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public:
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public:
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virtual ~X86AsmInstrumentation();
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// Tries to instrument and emit instruction.
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@ -40,10 +40,10 @@ class X86AsmInstrumentation {
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SmallVectorImpl<std::unique_ptr<MCParsedAsmOperand>> &Operands,
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MCContext &Ctx, const MCInstrInfo &MII, MCStreamer &Out);
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protected:
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friend X86AsmInstrumentation *CreateX86AsmInstrumentation(
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const MCTargetOptions &MCOptions, const MCContext &Ctx,
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const MCSubtargetInfo &STI);
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protected:
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friend X86AsmInstrumentation *
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CreateX86AsmInstrumentation(const MCTargetOptions &MCOptions,
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const MCContext &Ctx, const MCSubtargetInfo &STI);
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X86AsmInstrumentation(const MCSubtargetInfo &STI);
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@ -52,6 +52,6 @@ class X86AsmInstrumentation {
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const MCSubtargetInfo &STI;
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};
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} // End llvm namespace
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} // End llvm namespace
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#endif
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