6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-23 16:19:52 +00:00
Code Issues Projects Releases Wiki Activity

misched: Better handling of invalid latencies in the machine model

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-10-17 17:27:10 +00:00
parent a747a84add
commit fdd6fa89b9
2 changed files with 15 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
include/llvm/MC/MCSchedule.h
View File

@@ -54,10 +54,12 @@ struct MCWriteProcResEntry {
};
/// Specify the latency in cpu cycles for a particular scheduling class and def
/// index. Also identify the WriteResources of this def. When the operand
/// expands to a sequence of writes, this ID is the last write in the sequence.
/// index. -1 indicates an invalid latency. Heuristics would typically consider
/// an instruction with invalid latency to have infinite latency. Also identify
/// the WriteResources of this def. When the operand expands to a sequence of
/// writes, this ID is the last write in the sequence.
struct MCWriteLatencyEntry {
unsigned Cycles;
int Cycles;
unsigned WriteResourceID;
bool operator==(const MCWriteLatencyEntry &Other) const {