6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-09 10:31:14 +00:00
Code Issues Projects Releases Wiki Activity

Fix comments.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41947 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-09-14 01:57:02 +00:00
parent 5c70954d97
commit fdd9f006bc
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -157,8 +157,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
.addReg(PPC::R0, false, false, true), FrameIdx);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
// R11 = ADDI FI#
// Dest = LVX R0, R11
// R0 = ADDI FI#
// STVX VAL, 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),
@ -210,8 +210,8 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
BuildMI(MBB, MI, TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0);
} else if (RC == PPC::VRRCRegisterClass) {
// We don't have indexed addressing for vector loads. Emit:
// R11 = ADDI FI#
// Dest = LVX R0, R11
// R0 = ADDI FI#
// Dest = LVX 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
addFrameReference(BuildMI(MBB, MI, TII.get(PPC::ADDI), PPC::R0),