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[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern.

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Summary:
Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes.

The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite.
During review, we also found that some of the existing CodeGen tests were incorrect and fixed them:
* bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'.
* vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order.
* compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match.

The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case.

Reviewers: matheusalmeida, jacksprat

Reviewed By: matheusalmeida

Differential Revision: http://llvm-reviews.chandlerc.com/D3028

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203657 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-03-12 11:54:00 +00:00
parent d4517fa24d
commit fe6bd52bf2
7 changed files with 85 additions and 49 deletions
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5
test/CodeGen/Mips/msa/bitwise.ll
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@@ -990,9 +990,10 @@ define void @bsel_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b, <16 x i8>*
%6 = and <16 x i8> %2, %4
%7 = or <16 x i8> %5, %6
; bmnz is the same operation
; CHECK-DAG: bmnz.v [[R1]], [[R2]], [[R3]]
; (vselect Mask, IfSet, IfClr) -> (BMNZ IfClr, IfSet, Mask)
; CHECK-DAG: bmnz.v [[R2]], [[R1]], [[R3]]
store <16 x i8> %7, <16 x i8>* %c
; CHECK-DAG: st.b [[R1]], 0($4)
; CHECK-DAG: st.b [[R2]], 0($4)
ret void
; CHECK: .size bsel_v16i8