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ARM64: use 32-bit moves for constants where possible.

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If we know that a particular 64-bit constant has all high bits zero, then we
can rely on the fact that 32-bit ARM64 instructions automatically zero out the
high bits of an x-register. This gives the expansion logic less constraints to
satisfy and so sometimes allows it to pick better sequences.

Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a
32-bit MOVN to be used in @test8 soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206379 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2014-04-16 11:52:51 +00:00
parent ea9988a812
commit fef8e383eb
11 changed files with 63 additions and 47 deletions
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10
test/CodeGen/ARM64/patchpoint.ll
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@@ -67,11 +67,11 @@ define i64 @jscall_patchpoint_codegen2(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen2:
; CHECK: Ltmp
; CHECK: orr x{{.+}}, xzr, #0x6
; CHECK: orr w{{.+}}, wzr, #0x6
; CHECK-NEXT: str x{{.+}}, [sp, #24]
; CHECK-NEXT: orr w{{.+}}, wzr, #0x4
; CHECK-NEXT: str w{{.+}}, [sp, #16]
; CHECK-NEXT: orr x{{.+}}, xzr, #0x2
; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
; CHECK-NEXT: str x{{.+}}, [sp]
; CHECK: Ltmp
; CHECK-NEXT: movz x16, #65535, lsl #32
@@ -88,15 +88,15 @@ define i64 @jscall_patchpoint_codegen3(i64 %callee) {
entry:
; CHECK-LABEL: jscall_patchpoint_codegen3:
; CHECK: Ltmp
; CHECK: movz x{{.+}}, #10
; CHECK: movz w{{.+}}, #10
; CHECK-NEXT: str x{{.+}}, [sp, #48]
; CHECK-NEXT: orr w{{.+}}, wzr, #0x8
; CHECK-NEXT: str w{{.+}}, [sp, #36]
; CHECK-NEXT: orr x{{.+}}, xzr, #0x6
; CHECK-NEXT: orr w{{.+}}, wzr, #0x6
; CHECK-NEXT: str x{{.+}}, [sp, #24]
; CHECK-NEXT: orr w{{.+}}, wzr, #0x4
; CHECK-NEXT: str w{{.+}}, [sp, #16]
; CHECK-NEXT: orr x{{.+}}, xzr, #0x2
; CHECK-NEXT: orr w{{.+}}, wzr, #0x2
; CHECK-NEXT: str x{{.+}}, [sp]
; CHECK: Ltmp
; CHECK-NEXT: movz x16, #65535, lsl #32