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Switch from bytes to bits for alignment for consistency

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15974 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2004-08-21 20:14:13 +00:00
parent fae896999c
commit ff0a6e6aac
1 changed files with 5 additions and 10 deletions
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15
lib/Target/X86/X86RegisterInfo.td
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@@ -76,8 +76,8 @@ def : RegisterAliases<SP, [ESP]>; def : RegisterAliases<BP, [EBP]>;
// top-level register classes. The order specified in the register list is // top-level register classes. The order specified in the register list is
// implicitly defined to be the register allocation order. // implicitly defined to be the register allocation order.
// //
def R8 : RegisterClass<i8, 1, [AL, AH, CL, CH, DL, DH, BL, BH]>; def R8 : RegisterClass<i8, 8, [AL, AH, CL, CH, DL, DH, BL, BH]>;
def R16 : RegisterClass<i16, 2, [AX, CX, DX, SI, DI, BX, BP, SP]> { def R16 : RegisterClass<i16, 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
let Methods = [{ let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const { iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
@@ -88,7 +88,7 @@ def R16 : RegisterClass<i16, 2, [AX, CX, DX, SI, DI, BX, BP, SP]> {
}]; }];
} }
def R32 : RegisterClass<i32, 4, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> { def R32 : RegisterClass<i32, 32, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
let Methods = [{ let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const { iterator allocation_order_end(MachineFunction &MF) const {
if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr? if (hasFP(MF)) // Does the function dedicate EBP to being a frame ptr?
@@ -99,12 +99,7 @@ def R32 : RegisterClass<i32, 4, [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
}]; }];
} }
def RFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; def RFP : RegisterClass<f80, 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
// Floating point stack registers. // Floating point stack registers.
def RST : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>; def RST : RegisterClass<f80, 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>;
// Registers which cannot be allocated.
//def : RegisterClass<i16, 2, [EFLAGS]>;