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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-13 04:38:24 +00:00
Merging the linear scan register allocator in trunk. It currently passes most tests under test/Programs/SingleSource/Benchmarks/Shootout so development will continue on trunk. The allocator is not enabled by default. You will need to pass -regallo=linearscan to lli or llc to use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10103 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos
302
lib/CodeGen/LiveIntervalAnalysis.cpp
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302
lib/CodeGen/LiveIntervalAnalysis.cpp
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//===-- LiveIntervals.cpp - Live Interval Analysis ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass which is used
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// by the Linear Scan Register allocator. This pass linearizes the
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// basic blocks of the function in DFS order and uses the
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// LiveVariables pass to conservatively compute live intervals for
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// each virtual and physical register.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "liveintervals"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegInfo.h"
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#include "llvm/Support/CFG.h"
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#include "Support/Debug.h"
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#include "Support/DepthFirstIterator.h"
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#include "Support/Statistic.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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RegisterAnalysis<LiveIntervals> X("liveintervals",
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"Live Interval Analysis");
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Statistic<> numIntervals("liveintervals", "Number of intervals");
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};
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
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{
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AU.setPreservesAll();
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AU.addRequired<LiveVariables>();
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AU.addRequiredID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Register allocate the whole function
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///
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bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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DEBUG(std::cerr << "Machine Function\n");
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mf_ = &fn;
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tm_ = &fn.getTarget();
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mri_ = tm_->getRegisterInfo();
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lv_ = &getAnalysis<LiveVariables>();
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allocatableRegisters_.clear();
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mbbi2mbbMap_.clear();
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mi2iMap_.clear();
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r2iMap_.clear();
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r2iMap_.clear();
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intervals_.clear();
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// mark allocatable registers
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allocatableRegisters_.resize(MRegisterInfo::FirstVirtualRegister);
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// Loop over all of the register classes...
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for (MRegisterInfo::regclass_iterator
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rci = mri_->regclass_begin(), rce = mri_->regclass_end();
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rci != rce; ++rci) {
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// Loop over all of the allocatable registers in the function...
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for (TargetRegisterClass::iterator
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i = (*rci)->allocation_order_begin(*mf_),
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e = (*rci)->allocation_order_end(*mf_); i != e; ++i) {
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allocatableRegisters_[*i] = true; // The reg is allocatable!
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}
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}
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// number MachineInstrs
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unsigned miIndex = 0;
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for (MachineFunction::iterator mbb = mf_->begin(), mbbEnd = mf_->end();
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mbb != mbbEnd; ++mbb) {
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const std::pair<MachineBasicBlock*, unsigned>& entry =
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lv_->getMachineBasicBlockInfo(&*mbb);
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bool inserted = mbbi2mbbMap_.insert(std::make_pair(entry.second,
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entry.first)).second;
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assert(inserted && "multiple index -> MachineBasicBlock");
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for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
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mi != miEnd; ++mi) {
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inserted = mi2iMap_.insert(std::make_pair(*mi, miIndex)).second;
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assert(inserted && "multiple MachineInstr -> index mappings");
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++miIndex;
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}
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}
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computeIntervals();
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return true;
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}
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void LiveIntervals::printRegName(unsigned reg) const
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{
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if (reg < MRegisterInfo::FirstVirtualRegister)
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std::cerr << mri_->getName(reg);
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else
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std::cerr << '%' << reg;
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}
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void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned reg)
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{
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DEBUG(std::cerr << "\t\t\tregister: ";printRegName(reg); std::cerr << '\n');
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unsigned instrIndex = getInstructionIndex(*mi);
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LiveVariables::VarInfo& vi = lv_->getVarInfo(reg);
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Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
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// handle multiple definition case (machine instructions violating
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// ssa after phi-elimination
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if (r2iit != r2iMap_.end()) {
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unsigned ii = r2iit->second;
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Interval& interval = intervals_[ii];
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unsigned end = getInstructionIndex(mbb->back()) + 1;
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DEBUG(std::cerr << "\t\t\t\tadding range: ["
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<< instrIndex << ',' << end << "]\n");
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interval.addRange(instrIndex, end);
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DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
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}
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else {
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// add new interval
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intervals_.push_back(Interval(reg));
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Interval& interval = intervals_.back();
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// update interval index for this register
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r2iMap_[reg] = intervals_.size() - 1;
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for (MbbIndex2MbbMap::iterator
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it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
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it != itEnd; ++it) {
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unsigned liveBlockIndex = it->first;
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MachineBasicBlock* liveBlock = it->second;
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if (liveBlockIndex < vi.AliveBlocks.size() &&
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vi.AliveBlocks[liveBlockIndex]) {
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unsigned start = getInstructionIndex(liveBlock->front());
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unsigned end = getInstructionIndex(liveBlock->back()) + 1;
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DEBUG(std::cerr << "\t\t\t\tadding range: ["
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<< start << ',' << end << "]\n");
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interval.addRange(start, end);
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}
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}
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bool killedInDefiningBasicBlock = false;
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for (int i = 0, e = vi.Kills.size(); i != e; ++i) {
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MachineBasicBlock* killerBlock = vi.Kills[i].first;
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MachineInstr* killerInstr = vi.Kills[i].second;
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killedInDefiningBasicBlock |= mbb == killerBlock;
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unsigned start = (mbb == killerBlock ?
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instrIndex :
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getInstructionIndex(killerBlock->front()));
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unsigned end = getInstructionIndex(killerInstr) + 1;
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DEBUG(std::cerr << "\t\t\t\tadding range: ["
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<< start << ',' << end << "]\n");
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interval.addRange(start, end);
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}
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if (!killedInDefiningBasicBlock) {
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unsigned end = getInstructionIndex(mbb->back()) + 1;
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interval.addRange(instrIndex, end);
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}
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DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
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}
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}
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void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned reg)
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{
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DEBUG(std::cerr << "\t\t\tregister: ";printRegName(reg); std::cerr << '\n');
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unsigned start = getInstructionIndex(*mi);
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unsigned end = start;
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for (MachineBasicBlock::iterator e = mbb->end(); mi != e; ++mi) {
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for (LiveVariables::killed_iterator
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ki = lv_->dead_begin(*mi),
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ke = lv_->dead_end(*mi);
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ki != ke; ++ki) {
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if (reg == ki->second) {
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end = getInstructionIndex(ki->first) + 1;
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goto exit;
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}
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}
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for (LiveVariables::killed_iterator
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ki = lv_->killed_begin(*mi),
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ke = lv_->killed_end(*mi);
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ki != ke; ++ki) {
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if (reg == ki->second) {
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end = getInstructionIndex(ki->first) + 1;
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goto exit;
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}
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}
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}
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exit:
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assert(start < end && "did not find end of interval?");
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Reg2IntervalMap::iterator r2iit = r2iMap_.find(reg);
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if (r2iit != r2iMap_.end()) {
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unsigned ii = r2iit->second;
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Interval& interval = intervals_[ii];
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DEBUG(std::cerr << "\t\t\t\tadding range: ["
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<< start << ',' << end << "]\n");
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interval.addRange(start, end);
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DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
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}
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else {
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intervals_.push_back(Interval(reg));
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Interval& interval = intervals_.back();
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// update interval index for this register
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r2iMap_[reg] = intervals_.size() - 1;
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DEBUG(std::cerr << "\t\t\t\tadding range: ["
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<< start << ',' << end << "]\n");
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interval.addRange(start, end);
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DEBUG(std::cerr << "\t\t\t\t" << interval << '\n');
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}
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}
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void LiveIntervals::handleRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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unsigned reg)
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{
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if (reg < MRegisterInfo::FirstVirtualRegister) {
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if (allocatableRegisters_[reg]) {
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handlePhysicalRegisterDef(mbb, mi, reg);
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}
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}
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else {
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handleVirtualRegisterDef(mbb, mi, reg);
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}
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}
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unsigned LiveIntervals::getInstructionIndex(MachineInstr* instr) const
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{
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assert(mi2iMap_.find(instr) != mi2iMap_.end() &&
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"instruction not assigned a number");
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return mi2iMap_.find(instr)->second;
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}
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/// computeIntervals - computes the live intervals for virtual
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/// registers. for some ordering of the machine instructions [1,N] a
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/// live interval is an interval [i, j] where 1 <= i <= j <= N for
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/// which a variable is live
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void LiveIntervals::computeIntervals()
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{
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DEBUG(std::cerr << "computing live intervals:\n");
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for (MbbIndex2MbbMap::iterator
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it = mbbi2mbbMap_.begin(), itEnd = mbbi2mbbMap_.end();
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it != itEnd; ++it) {
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MachineBasicBlock* mbb = it->second;
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DEBUG(std::cerr << "machine basic block: "
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<< mbb->getBasicBlock()->getName() << "\n");
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for (MachineBasicBlock::iterator mi = mbb->begin(), miEnd = mbb->end();
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mi != miEnd; ++mi) {
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MachineInstr* instr = *mi;
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const TargetInstrDescriptor& tid =
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tm_->getInstrInfo().get(instr->getOpcode());
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DEBUG(std::cerr << "\t\tinstruction["
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<< getInstructionIndex(instr) << "]: ";
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instr->print(std::cerr, *tm_););
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// handle implicit defs
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for (const unsigned* id = tid.ImplicitDefs; *id; ++id) {
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unsigned physReg = *id;
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handlePhysicalRegisterDef(mbb, mi, physReg);
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}
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// handle explicit defs
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for (int i = instr->getNumOperands() - 1; i >= 0; --i) {
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MachineOperand& mop = instr->getOperand(i);
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if (!mop.isVirtualRegister())
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continue;
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if (mop.opIsDefOnly() || mop.opIsDefAndUse()) {
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unsigned reg = mop.getAllocatedRegNum();
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handleVirtualRegisterDef(mbb, mi, reg);
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}
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}
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}
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}
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DEBUG(std::copy(intervals_.begin(), intervals_.end(),
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std::ostream_iterator<Interval>(std::cerr, "\n")));
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}
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