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TBAA: remove !tbaa from testing cases if not used.

Browse Source 
This will make it easier to turn on struct-path aware TBAA since the metadata
format will change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Manman Ren
2013-04-29 22:58:55 +00:00
parent ad96c64355
commit ff6222ef2f
11 changed files with 32 additions and 69 deletions
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9
test/CodeGen/ARM/2011-12-14-machine-sink.ll
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@ -15,13 +15,13 @@ for.cond: ; preds = %for.body, %entry
for.body: ; preds = %for.cond for.body: ; preds = %for.cond
%v.5 = select i1 undef, i32 undef, i32 0 %v.5 = select i1 undef, i32 undef, i32 0
%0 = load i8* undef, align 1, !tbaa !0 %0 = load i8* undef, align 1
%conv88 = zext i8 %0 to i32 %conv88 = zext i8 %0 to i32
%sub89 = sub nsw i32 0, %conv88 %sub89 = sub nsw i32 0, %conv88
%v.8 = select i1 undef, i32 undef, i32 %sub89 %v.8 = select i1 undef, i32 undef, i32 %sub89
%1 = load i8* null, align 1, !tbaa !0 %1 = load i8* null, align 1
%conv108 = zext i8 %1 to i32 %conv108 = zext i8 %1 to i32
%2 = load i8* undef, align 1, !tbaa !0 %2 = load i8* undef, align 1
%conv110 = zext i8 %2 to i32 %conv110 = zext i8 %2 to i32
%sub111 = sub nsw i32 %conv108, %conv110 %sub111 = sub nsw i32 %conv108, %conv110
%cmp112 = icmp slt i32 %sub111, 0 %cmp112 = icmp slt i32 %sub111, 0
@ -44,6 +44,3 @@ if.end299: ; preds = %for.body, %for.cond
%s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ] %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ]
ret i32 %s.10 ret i32 %s.10
} }
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}

18
test/CodeGen/ARM/2012-01-23-PostRA-LICM.ll
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@ -18,7 +18,7 @@ bb3: ; preds = %bb4, %bb2
br i1 %tmp, label %bb4, label %bb67 br i1 %tmp, label %bb4, label %bb67
bb4: ; preds = %bb3 bb4: ; preds = %bb3
%tmp5 = load <4 x i32>* undef, align 16, !tbaa !0 %tmp5 = load <4 x i32>* undef, align 16
%tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607> %tmp6 = and <4 x i32> %tmp5, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
%tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216> %tmp7 = or <4 x i32> %tmp6, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
%tmp8 = bitcast <4 x i32> %tmp7 to <4 x float> %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>
@ -41,9 +41,9 @@ bb4: ; preds = %bb3
%tmp24 = trunc i128 %tmp23 to i64 %tmp24 = trunc i128 %tmp23 to i64
%tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0
%tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1
%tmp27 = load float* undef, align 4, !tbaa !2 %tmp27 = load float* undef, align 4
%tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3
%tmp29 = load <4 x i32>* undef, align 16, !tbaa !0 %tmp29 = load <4 x i32>* undef, align 16
%tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607> %tmp30 = and <4 x i32> %tmp29, <i32 8388607, i32 8388607, i32 8388607, i32 8388607>
%tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216> %tmp31 = or <4 x i32> %tmp30, <i32 1065353216, i32 1065353216, i32 1065353216, i32 1065353216>
%tmp32 = bitcast <4 x i32> %tmp31 to <4 x float> %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>
@ -52,10 +52,10 @@ bb4: ; preds = %bb3
%tmp35 = fmul <4 x float> %tmp34, undef %tmp35 = fmul <4 x float> %tmp34, undef
%tmp36 = fmul <4 x float> %tmp35, undef %tmp36 = fmul <4 x float> %tmp35, undef
%tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
%tmp38 = load float* undef, align 4, !tbaa !2 %tmp38 = load float* undef, align 4
%tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0
%tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
%tmp41 = load float* undef, align 4, !tbaa !2 %tmp41 = load float* undef, align 4
%tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3
%tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer
%tmp44 = fmul <4 x float> %tmp33, %tmp43 %tmp44 = fmul <4 x float> %tmp33, %tmp43
@ -64,10 +64,10 @@ bb4: ; preds = %bb3
%tmp47 = fmul <4 x float> %tmp46, %tmp36 %tmp47 = fmul <4 x float> %tmp46, %tmp36
%tmp48 = fadd <4 x float> undef, %tmp47 %tmp48 = fadd <4 x float> undef, %tmp47
%tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
%tmp50 = load float* undef, align 4, !tbaa !2 %tmp50 = load float* undef, align 4
%tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3
%tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind
%tmp54 = load float* %tmp52, align 4, !tbaa !2 %tmp54 = load float* %tmp52, align 4
%tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3
%tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22 %tmp56 = fsub <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %tmp22
%tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
@ -99,7 +99,3 @@ declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwin
declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}
!2 = metadata !{metadata !"float", metadata !0}

5
test/CodeGen/ARM/2012-01-24-RegSequenceLiveRange.ll
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@ -7,7 +7,7 @@ target triple = "armv7-none-linux-eabi"
; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE. ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 { define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
bb: bb:
%tmp = load <2 x float>* undef, align 8, !tbaa !0 %tmp = load <2 x float>* undef, align 8
%tmp2 = extractelement <2 x float> %tmp, i32 0 %tmp2 = extractelement <2 x float> %tmp, i32 0
%tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
%tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
@ -70,6 +70,3 @@ entry:
declare arm_aapcs_vfpcc void @bar(i8*, float, float, float) declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}

9
test/CodeGen/ARM/2012-01-26-CopyPropKills.ll
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@ -56,9 +56,9 @@ bb3: ; preds = %bb2
%tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer
%tmp40 = bitcast <1 x i64> %tmp39 to <2 x float> %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float>
%tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%tmp42 = load <4 x float>* null, align 16, !tbaa !0 %tmp42 = load <4 x float>* null, align 16
%tmp43 = fmul <4 x float> %tmp42, %tmp41 %tmp43 = fmul <4 x float> %tmp42, %tmp41
%tmp44 = load <4 x float>* undef, align 16, !tbaa !0 %tmp44 = load <4 x float>* undef, align 16
%tmp45 = fadd <4 x float> undef, %tmp43 %tmp45 = fadd <4 x float> undef, %tmp43
%tmp46 = fadd <4 x float> undef, %tmp45 %tmp46 = fadd <4 x float> undef, %tmp45
%tmp47 = bitcast <4 x float> %tmp36 to <2 x i64> %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64>
@ -108,7 +108,7 @@ bb3: ; preds = %bb2
%tmp89 = fmul <4 x float> undef, %tmp88 %tmp89 = fmul <4 x float> undef, %tmp88
%tmp90 = fadd <4 x float> %tmp89, undef %tmp90 = fadd <4 x float> %tmp89, undef
%tmp91 = fadd <4 x float> undef, %tmp90 %tmp91 = fadd <4 x float> undef, %tmp90
store <4 x float> %tmp91, <4 x float>* undef, align 16, !tbaa !0 store <4 x float> %tmp91, <4 x float>* undef, align 16
unreachable unreachable
bb92: ; preds = %bb2 bb92: ; preds = %bb2
@ -116,6 +116,3 @@ bb92: ; preds = %bb2
} }
declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret, [8 x i64]) nounwind uwtable inlinehint declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret, [8 x i64]) nounwind uwtable inlinehint
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}

11
test/CodeGen/ARM/2012-04-02-TwoAddrInstrCrash.ll
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@ -9,16 +9,13 @@ define arm_aapcs_vfpcc void @foo() nounwind align 2 {
; <label>:1 ; preds = %0 ; <label>:1 ; preds = %0
%2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1> %2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
%3 = bitcast <2 x i64> %2 to <4 x float> %3 = bitcast <2 x i64> %2 to <4 x float>
store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0 store <4 x float> zeroinitializer, <4 x float>* undef, align 16
store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0 store <4 x float> zeroinitializer, <4 x float>* undef, align 16
store <4 x float> %3, <4 x float>* undef, align 16, !tbaa !0 store <4 x float> %3, <4 x float>* undef, align 16
%4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2 %4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2
store <4 x float> %4, <4 x float>* undef, align 16, !tbaa !0 store <4 x float> %4, <4 x float>* undef, align 16
unreachable unreachable
; <label>:5 ; preds = %0 ; <label>:5 ; preds = %0
ret void ret void
} }
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}

5
test/CodeGen/ARM/2012-04-10-DAGCombine.ll
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@ -20,12 +20,9 @@ bb5: ; preds = %bb4
%tmp15 = shufflevector <2 x float> %tmp14, <2 x float> undef, <4 x i32> zeroinitializer %tmp15 = shufflevector <2 x float> %tmp14, <2 x float> undef, <4 x i32> zeroinitializer
%tmp16 = fmul <4 x float> zeroinitializer, %tmp15 %tmp16 = fmul <4 x float> zeroinitializer, %tmp15
%tmp17 = fadd <4 x float> %tmp16, %arg %tmp17 = fadd <4 x float> %tmp16, %arg
store <4 x float> %tmp17, <4 x float>* undef, align 8, !tbaa !0 store <4 x float> %tmp17, <4 x float>* undef, align 8
br label %bb18 br label %bb18
bb18: ; preds = %bb5, %bb4 bb18: ; preds = %bb5, %bb4
ret void ret void
} }
!0 = metadata !{metadata !"omnipotent char", metadata !1}
!1 = metadata !{metadata !"Simple C/C++ TBAA", null}

12
test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll
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@ -26,18 +26,14 @@
; CHECK: Successors: ; CHECK: Successors:
define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
entry: entry:
store volatile i32 65540, i32* %p1, align 4, !tbaa !0 store volatile i32 65540, i32* %p1, align 4
%0 = load volatile i32* %p2, align 4, !tbaa !0 %0 = load volatile i32* %p2, align 4
ret i32 %0 ret i32 %0
} }
define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind { define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
entry: entry:
store i32 65540, i32* %p1, align 4, !tbaa !0 store i32 65540, i32* %p1, align 4
%0 = load i32* %p2, align 4, !tbaa !0 %0 = load i32* %p2, align 4
ret i32 %0 ret i32 %0
} }
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}

8
test/CodeGen/ARM/2012-08-04-DtripleSpillReload.ll
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@ -129,7 +129,7 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
%45 = fmul <4 x float> undef, undef %45 = fmul <4 x float> undef, undef
%46 = fmul <4 x float> %45, %43 %46 = fmul <4 x float> %45, %43
%47 = fmul <4 x float> undef, %44 %47 = fmul <4 x float> undef, %44
%48 = load <4 x float>* undef, align 8, !tbaa !1 %48 = load <4 x float>* undef, align 8
%49 = bitcast <4 x float> %48 to <2 x i64> %49 = bitcast <4 x float> %48 to <2 x i64>
%50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1> %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32> <i32 1>
%51 = bitcast <1 x i64> %50 to <2 x float> %51 = bitcast <1 x i64> %50 to <2 x float>
@ -145,10 +145,10 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
%61 = fmul <4 x float> %59, %60 %61 = fmul <4 x float> %59, %60
%62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01> %62 = fmul <4 x float> %61, <float 6.000000e+01, float 6.000000e+01, float 6.000000e+01, float 6.000000e+01>
%63 = fadd <4 x float> %47, %62 %63 = fadd <4 x float> %47, %62
store <4 x float> %46, <4 x float>* undef, align 8, !tbaa !1 store <4 x float> %46, <4 x float>* undef, align 8
call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
store <4 x float> %63, <4 x float>* undef, align 8, !tbaa !1 store <4 x float> %63, <4 x float>* undef, align 8
unreachable unreachable
; <label>:64 ; preds = %41, %40 ; <label>:64 ; preds = %41, %40
@ -170,5 +170,3 @@ define arm_aapcs_vfpcc void @foo(float, i1 zeroext, i1 zeroext) nounwind uwtable
declare arm_aapcs_vfpcc void @bar(%0*, float) declare arm_aapcs_vfpcc void @bar(%0*, float)
!0 = metadata !{metadata !"branch_weights", i32 64, i32 4} !0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}

10
test/CodeGen/ARM/2013-01-21-PR14992.ll
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@ -6,11 +6,11 @@
;CHECK: foo: ;CHECK: foo:
define i32 @foo(i32* %a) nounwind optsize { define i32 @foo(i32* %a) nounwind optsize {
entry: entry:
%0 = load i32* %a, align 4, !tbaa !0 %0 = load i32* %a, align 4
%arrayidx1 = getelementptr inbounds i32* %a, i32 1 %arrayidx1 = getelementptr inbounds i32* %a, i32 1
%1 = load i32* %arrayidx1, align 4, !tbaa !0 %1 = load i32* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32* %a, i32 2 %arrayidx2 = getelementptr inbounds i32* %a, i32 2
%2 = load i32* %arrayidx2, align 4, !tbaa !0 %2 = load i32* %arrayidx2, align 4
%add.ptr = getelementptr inbounds i32* %a, i32 3 %add.ptr = getelementptr inbounds i32* %a, i32 3
;Make sure we do not have a duplicated register in the front of the reg list ;Make sure we do not have a duplicated register in the front of the reg list
;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}}, ;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
@ -22,7 +22,3 @@ entry:
} }
declare void @bar(i32*) optsize declare void @bar(i32*) optsize
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}

8
test/CodeGen/ARM/commute-movcc.ll
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@ -32,7 +32,7 @@ for.body: ; preds = %entry, %if.end8
%BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ] %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ]
%BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ] %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ]
%arrayidx = getelementptr inbounds i32* %a, i32 %i.012 %arrayidx = getelementptr inbounds i32* %a, i32 %i.012
%0 = load i32* %arrayidx, align 4, !tbaa !0 %0 = load i32* %arrayidx, align 4
%mul = mul i32 %0, %0 %mul = mul i32 %0, %0
%sub = add nsw i32 %i.012, -5 %sub = add nsw i32 %i.012, -5
%cmp2 = icmp eq i32 %sub, %Pref %cmp2 = icmp eq i32 %sub, %Pref
@ -53,7 +53,7 @@ if.else: ; preds = %for.body
if.end8: ; preds = %if.else, %if.then if.end8: ; preds = %if.else, %if.then
%BestIdx.1 = phi i32 [ %i.0.BestIdx.0, %if.then ], [ %BestIdx.0.i.0, %if.else ] %BestIdx.1 = phi i32 [ %i.0.BestIdx.0, %if.then ], [ %BestIdx.0.i.0, %if.else ]
%BestCost.1 = phi i32 [ %mul.BestCost.0, %if.then ], [ %BestCost.0.mul, %if.else ] %BestCost.1 = phi i32 [ %mul.BestCost.0, %if.then ], [ %BestCost.0.mul, %if.else ]
store i32 %mul, i32* %arrayidx, align 4, !tbaa !0 store i32 %mul, i32* %arrayidx, align 4
%inc = add i32 %i.012, 1 %inc = add i32 %i.012, 1
%cmp = icmp eq i32 %inc, 11 %cmp = icmp eq i32 %inc, 11
br i1 %cmp, label %for.end, label %for.body br i1 %cmp, label %for.end, label %for.body
@ -61,7 +61,3 @@ if.end8: ; preds = %if.else, %if.then
for.end: ; preds = %if.end8 for.end: ; preds = %if.end8
ret i32 %BestIdx.1 ret i32 %BestIdx.1
} }
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA", null}

6
test/CodeGen/ARM/ehabi-filters.ll
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@ -19,7 +19,7 @@ define i32 @main() {
entry: entry:
%exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
%0 = bitcast i8* %exception.i to i32* %0 = bitcast i8* %exception.i to i32*
store i32 42, i32* %0, align 4, !tbaa !0 store i32 42, i32* %0, align 4
invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn
to label %unreachable.i unwind label %lpad.i to label %unreachable.i unwind label %lpad.i
@ -71,7 +71,3 @@ declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
declare i8* @__cxa_begin_catch(i8*) declare i8* @__cxa_begin_catch(i8*)
declare void @__cxa_end_catch() declare void @__cxa_end_catch()
!0 = metadata !{metadata !"int", metadata !1}
!1 = metadata !{metadata !"omnipotent char", metadata !2}
!2 = metadata !{metadata !"Simple C/C++ TBAA"}