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Added pslldq and psrldq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27412 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -57,6 +57,11 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{
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return N->isExactlyValue(+0.0);
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}]>;
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def PSxLDQ_imm : SDNodeXForm<imm, [{
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// Transformation function: imm >> 3
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return getI32Imm(N->getValue() >> 3);
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}]>;
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// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUFP* etc. imm.
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def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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@ -1159,6 +1164,13 @@ def PSUBQrm : PDI<0xFB, MRMSrcMem, (ops VR128:$dst, VR128:$src1, f128mem:$src2),
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(load addr:$src2))))]>;
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}
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let isTwoAddress = 1 in {
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def PSLLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
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"pslldq {$src2, $dst|$dst, $src2}", []>;
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def PSRLDQri : PDIi8<0x73, MRM7r, (ops VR128:$dst, VR128:$src1, i32i8imm:$src2),
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"psrldq {$src2, $dst|$dst, $src2}", []>;
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}
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// Logical
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let isTwoAddress = 1 in {
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let isCommutable = 1 in {
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@ -1721,6 +1733,12 @@ def : Pat<(vector_shuffle (loadv4f32 addr:$src1), (undef),
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(v4f32 (PSHUFLWmi addr:$src1, PSHUFLW_fp_shuffle_mask:$sm))>,
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Requires<[HasSSE2]>;
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// 128-bit logical shifts
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def : Pat<(int_x86_sse2_psll_dq VR128:$src1, imm:$src2),
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(v2i64 (PSLLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
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def : Pat<(int_x86_sse2_psrl_dq VR128:$src1, imm:$src2),
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(v2i64 (PSRLDQri VR128:$src1, (PSxLDQ_imm imm:$src2)))>;
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// Logical ops
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def : Pat<(and (bc_v4i32 (v4f32 VR128:$src1)), (loadv4i32 addr:$src2)),
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(ANDPSrm VR128:$src1, addr:$src2)>;
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