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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-28 04:33:05 +00:00
Eliminate X86ISD::TEST, using X86ISD::CMP instead. Match X86ISD::CMP patterns
using test, which provides nice simplifications like:
- movl %edi, %ecx
- andl $2, %ecx
- cmpl $0, %ecx
+ testl $2, %edi
je LBB1_11 #cond_next90
There are a couple of dagiselemitter deficiencies that this exposes, they will
be handled later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30156 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
b14ca605d7
commit
ffc0b2663e
@ -2836,8 +2836,11 @@ SDOperand X86TargetLowering::LowerShift(SDOperand Op, SelectionDAG &DAG) {
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Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, MVT::i32, ShOpHi, ShAmt);
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}
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SDOperand InFlag = DAG.getNode(X86ISD::TEST, MVT::Flag,
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ShAmt, DAG.getConstant(32, MVT::i8));
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SDOperand InFlag =
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DAG.getNode(X86ISD::CMP, MVT::Flag,
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DAG.getNode(ISD::AND, MVT::i8,
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ShAmt, DAG.getConstant(32, MVT::i8)),
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DAG.getConstant(0, MVT::i8));
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SDOperand Hi, Lo;
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SDOperand CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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@ -3134,7 +3137,8 @@ SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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if (addTest) {
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CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Op0,
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DAG.getConstant(0, MVT::i8));
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}
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std::vector<MVT::ValueType> Tys;
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@ -3190,7 +3194,8 @@ SDOperand X86TargetLowering::LowerBRCOND(SDOperand Op, SelectionDAG &DAG) {
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if (addTest) {
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CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
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Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Cond, Cond);
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Cond = DAG.getNode(X86ISD::CMP, MVT::Flag, Cond,
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DAG.getConstant(0, MVT::i8));
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}
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return DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
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Op.getOperand(0), Op.getOperand(2), CC, Cond);
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@ -3774,7 +3779,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::TAILCALL: return "X86ISD::TAILCALL";
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case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG";
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case X86ISD::CMP: return "X86ISD::CMP";
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case X86ISD::TEST: return "X86ISD::TEST";
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case X86ISD::COMI: return "X86ISD::COMI";
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case X86ISD::UCOMI: return "X86ISD::UCOMI";
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case X86ISD::SETCC: return "X86ISD::SETCC";
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@ -52,8 +52,6 @@ def X86shrd : SDNode<"X86ISD::SHRD", SDTIntShiftDOp>;
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def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest,
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[SDNPOutFlag]>;
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def X86test : SDNode<"X86ISD::TEST", SDTX86CmpTest,
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[SDNPOutFlag]>;
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def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov,
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[SDNPInFlag, SDNPOutFlag]>;
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@ -2073,60 +2071,54 @@ def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
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let isCommutable = 1 in { // TEST X, Y --> TEST Y, X
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def TEST8rr : I<0x84, MRMDestReg, (ops GR8:$src1, GR8:$src2),
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"test{b} {$src2, $src1|$src1, $src2}",
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[(X86test GR8:$src1, GR8:$src2)]>;
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[(X86cmp (and GR8:$src1, GR8:$src2), 0)]>;
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def TEST16rr : I<0x85, MRMDestReg, (ops GR16:$src1, GR16:$src2),
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"test{w} {$src2, $src1|$src1, $src2}",
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[(X86test GR16:$src1, GR16:$src2)]>, OpSize;
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[(X86cmp (and GR16:$src1, GR16:$src2), 0)]>, OpSize;
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def TEST32rr : I<0x85, MRMDestReg, (ops GR32:$src1, GR32:$src2),
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"test{l} {$src2, $src1|$src1, $src2}",
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[(X86test GR32:$src1, GR32:$src2)]>;
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[(X86cmp (and GR32:$src1, GR32:$src2), 0)]>;
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}
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def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, GR8 :$src2),
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"test{b} {$src2, $src1|$src1, $src2}",
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[(X86test (loadi8 addr:$src1), GR8:$src2)]>;
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def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, GR16:$src2),
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"test{w} {$src2, $src1|$src1, $src2}",
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[(X86test (loadi16 addr:$src1), GR16:$src2)]>,
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OpSize;
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def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, GR32:$src2),
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"test{l} {$src2, $src1|$src1, $src2}",
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[(X86test (loadi32 addr:$src1), GR32:$src2)]>;
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// FIXME: These patterns are disabled until isel issue surrounding
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//CodeGen/X86/test-load-fold.ll is fixed.
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def TEST8rm : I<0x84, MRMSrcMem, (ops GR8 :$src1, i8mem :$src2),
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"test{b} {$src2, $src1|$src1, $src2}",
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[(X86test GR8:$src1, (loadi8 addr:$src2))]>;
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[/*(X86cmp (and GR8:$src1, (loadi8 addr:$src2)), 0)*/]>;
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def TEST16rm : I<0x85, MRMSrcMem, (ops GR16:$src1, i16mem:$src2),
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"test{w} {$src2, $src1|$src1, $src2}",
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[(X86test GR16:$src1, (loadi16 addr:$src2))]>,
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[/*(X86cmp (and GR16:$src1, (loadi16 addr:$src2)), 0)*/]>,
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OpSize;
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def TEST32rm : I<0x85, MRMSrcMem, (ops GR32:$src1, i32mem:$src2),
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"test{l} {$src2, $src1|$src1, $src2}",
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[(X86test GR32:$src1, (loadi32 addr:$src2))]>;
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[/*(X86cmp (and GR32:$src1, (loadi32 addr:$src2)), 0)*/]>;
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def TEST8ri : Ii8 <0xF6, MRM0r, // flags = GR8 & imm8
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(ops GR8:$src1, i8imm:$src2),
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"test{b} {$src2, $src1|$src1, $src2}",
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[(X86test GR8:$src1, imm:$src2)]>;
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[(X86cmp (and GR8:$src1, imm:$src2), 0)]>;
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def TEST16ri : Ii16<0xF7, MRM0r, // flags = GR16 & imm16
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(ops GR16:$src1, i16imm:$src2),
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"test{w} {$src2, $src1|$src1, $src2}",
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[(X86test GR16:$src1, imm:$src2)]>, OpSize;
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[(X86cmp (and GR16:$src1, imm:$src2), 0)]>, OpSize;
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def TEST32ri : Ii32<0xF7, MRM0r, // flags = GR32 & imm32
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(ops GR32:$src1, i32imm:$src2),
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"test{l} {$src2, $src1|$src1, $src2}",
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[(X86test GR32:$src1, imm:$src2)]>;
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[(X86cmp (and GR32:$src1, imm:$src2), 0)]>;
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// FIXME: These patterns are disabled until isel issue surrounding
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//CodeGen/X86/test-load-fold.ll is fixed.
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def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8
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(ops i8mem:$src1, i8imm:$src2),
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"test{b} {$src2, $src1|$src1, $src2}",
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[(X86test (loadi8 addr:$src1), imm:$src2)]>;
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[/*(X86cmp (and (loadi8 addr:$src1), imm:$src2), 0)*/]>;
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def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16
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(ops i16mem:$src1, i16imm:$src2),
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"test{w} {$src2, $src1|$src1, $src2}",
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[(X86test (loadi16 addr:$src1), imm:$src2)]>,
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[/*(X86cmp (and (loadi16 addr:$src1), imm:$src2), 0)*/]>,
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OpSize;
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def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32
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(ops i32mem:$src1, i32imm:$src2),
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"test{l} {$src2, $src1|$src1, $src2}",
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[(X86test (loadi32 addr:$src1), imm:$src2)]>;
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[/*(X86cmp (and (loadi32 addr:$src1), imm:$src2), 0)*/]>;
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// Condition code ops, incl. set if equal/not equal/...
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@ -2523,6 +2515,16 @@ def : Pat<(truncstore (i8 imm:$src), addr:$dst, i1),
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def : Pat<(truncstore GR8:$src, addr:$dst, i1),
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(MOV8mr addr:$dst, GR8:$src)>;
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// Comparisons.
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// TEST R,R is smaller than CMP R,0
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def : Pat<(X86cmp GR8:$src1, 0),
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(TEST8rr GR8:$src1, GR8:$src1)>;
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def : Pat<(X86cmp GR16:$src1, 0),
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(TEST16rr GR16:$src1, GR16:$src1)>;
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def : Pat<(X86cmp GR32:$src1, 0),
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(TEST32rr GR32:$src1, GR32:$src1)>;
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// {s|z}extload bool -> {s|z}extload byte
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def : Pat<(sextloadi16i1 addr:$src), (MOVSX16rm8 addr:$src)>;
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def : Pat<(sextloadi32i1 addr:$src), (MOVSX32rm8 addr:$src)>;
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