From fff6c5332f748d477e6ad0bd9b60b49ae867ab42 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Thu, 22 Apr 2010 23:14:21 +0000 Subject: [PATCH] Add an initial description of a new concept: trap values, and change the definition of the nsw and nuw flags to make use of it. nsw was introduced to help optimizers answer yes to the following: // Can we change i from i32 to i64 to eliminate the cast inside the loop? for (int i = 0; i < n; ++i) A[i] *= 0.1; // Can we assume that this loop will eventually terminate? for (int i = 0; i <= n; ++i) A[i] *= 0.1; In its current form, it isn't truly sufficient for either. In the first case, if the increment overflows, it'll still have some valid i32 value; sign-extending it will produce a value which is 33 homogeneous sign bits trailed by 31 independent undef bits. If i is promoted to i64, it won't have those same values when it reaches that point. (The compiler could recover here by reasoning about how i is used by the load, but that's a lot more complicated and isn't always possible.) In the second case, there is no value for i which will be greater than n, so having the increment return undef on overflow doesn't help. Trap values are a formalization of some existing concepts that we have about LLVM IR, and give the optimizers a better basis for answering yes to both questions above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102140 91177308-0d34-0410-b5e6-96231b3b80d8 --- docs/LangRef.html | 38 +++++++++++++++++++++++++++++++++++--- 1 file changed, 35 insertions(+), 3 deletions(-) diff --git a/docs/LangRef.html b/docs/LangRef.html index 1b94ab5a9a7..8c52a2118eb 100644 --- a/docs/LangRef.html +++ b/docs/LangRef.html @@ -89,6 +89,7 @@
  • Complex Constants
  • Global Variable and Function Addresses
  • Undefined Values
  • +
  • Trap Values
  • Addresses of Basic Blocks
  • Constant Expressions
  • @@ -2302,6 +2303,34 @@ has undefined behavior.

    + +
    Trap Values
    +
    + +

    Trap values are similar to undef values, however + instead of representing an unspecified bit pattern, they represent the + fact that an instruction or constant expression which cannot evoke side + effects has nevertheless detected a condition which results in undefined + behavior.

    + +

    Any non-void instruction or constant expression other than non-intrinsic + calls or invokes with a trap operand has trap as its result value. + Any instruction with a trap operand which may have side effects emits + those side effects as if it had an undef operand instead.

    + +

    For example, an and of a trap value with + zero still has a trap value result. Using that value as an index in a + getelementptr yields a trap + result. Using that result as the address of a + store produces undefined behavior.

    + +

    There is currently no way of representing a trap constant in the IR; they + only exist when produced by certain instructions, such as an + add with the nsw flag + set, when overflow occurs.

    + +
    +
    Addresses of Basic Blocks
    @@ -3104,7 +3133,8 @@ Instruction

    nuw and nsw stand for "No Unsigned Wrap" and "No Signed Wrap", respectively. If the nuw and/or nsw keywords are present, the result value of the add - is undefined if unsigned and/or signed overflow, respectively, occurs.

    + is a trap value if unsigned and/or signed overflow, + respectively, occurs.

    Example:
    @@ -3184,7 +3214,8 @@ Instruction 
     

    nuw and nsw stand for "No Unsigned Wrap" and "No Signed Wrap", respectively. If the nuw and/or nsw keywords are present, the result value of the sub - is undefined if unsigned and/or signed overflow, respectively, occurs.

    + is a trap value if unsigned and/or signed overflow, + respectively, occurs.

    Example:
    @@ -3270,7 +3301,8 @@ Instruction 
     

    nuw and nsw stand for "No Unsigned Wrap" and "No Signed Wrap", respectively. If the nuw and/or nsw keywords are present, the result value of the mul - is undefined if unsigned and/or signed overflow, respectively, occurs.

    + is a trap value if unsigned and/or signed overflow, + respectively, occurs.

    Example: