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Author SHA1 Message Date
Alex Lorenz
d0ef9f3115 MIR Parser: Verify the implicit machine register operands. 
This commit verifies that the parsed machine instructions contain the implicit
register operands as specified by the MCInstrDesc. Variadic and call
instructions aren't verified.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10781


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241537 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-07-07 02:08:46 +00:00