33938 Commits

Author SHA1 Message Date
7ffec838a2 Protection against stack-based memory corruption errors using SafeStack
This patch adds the safe stack instrumentation pass to LLVM, which separates
the program stack into a safe stack, which stores return addresses, register
spills, and local variables that are statically verified to be accessed
in a safe way, and the unsafe stack, which stores everything else. Such
separation makes it much harder for an attacker to corrupt objects on the
safe stack, including function pointers stored in spilled registers and
return addresses. You can find more information about the safe stack, as
well as other parts of or control-flow hijack protection technique in our
OSDI paper on code-pointer integrity (http://dslab.epfl.ch/pubs/cpi.pdf)
and our project website (http://levee.epfl.ch).

The overhead of our implementation of the safe stack is very close to zero
(0.01% on the Phoronix benchmarks). This is lower than the overhead of
stack cookies, which are supported by LLVM and are commonly used today,
yet the security guarantees of the safe stack are strictly stronger than
stack cookies. In some cases, the safe stack improves performance due to
better cache locality.

Our current implementation of the safe stack is stable and robust, we
used it to recompile multiple projects on Linux including Chromium, and
we also recompiled the entire FreeBSD user-space system and more than 100
packages. We ran unit tests on the FreeBSD system and many of the packages
and observed no errors caused by the safe stack. The safe stack is also fully
binary compatible with non-instrumented code and can be applied to parts of
a program selectively.

This patch is our implementation of the safe stack on top of LLVM. The
patches make the following changes:

- Add the safestack function attribute, similar to the ssp, sspstrong and
  sspreq attributes.

- Add the SafeStack instrumentation pass that applies the safe stack to all
  functions that have the safestack attribute. This pass moves all unsafe local
  variables to the unsafe stack with a separate stack pointer, whereas all
  safe variables remain on the regular stack that is managed by LLVM as usual.

- Invoke the pass as the last stage before code generation (at the same time
  the existing cookie-based stack protector pass is invoked).

- Add unit tests for the safe stack.

Original patch by Volodymyr Kuznetsov and others at the Dependable Systems
Lab at EPFL; updates and upstreaming by myself.

Differential Revision: http://reviews.llvm.org/D6094

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239761 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 21:07:11 +00:00
a15d888abf MIR Serialization: Connect the machine function analysis pass to the MIR parser.
This commit connects the machine function analysis pass (which creates machine
functions) to the MIR parser, which will initialize the machine functions 
with the state from the MIR file and reconstruct the machine IR.

This commit introduces a new interface called 'MachineFunctionInitializer',
which can be used to provide custom initialization for the machine functions.

This commit also introduces a new diagnostic class called 
'DiagnosticInfoMIRParser' which is used for MIR parsing errors.
This commit modifies the default diagnostic handling in LLVMContext - now the
the diagnostics are printed directly into llvm::errs() so that the MIR parsing 
errors can be printed with colours.  

Reviewers: Justin Bogner

Differential Revision: http://reviews.llvm.org/D9928


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239753 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 20:30:22 +00:00
e99f30c57b Remove duplicate conditional in if-stmt.
Fixes PR23839.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239751 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 20:16:53 +00:00
cf9ca4fd5d [Hexagon] Moving pass declarations out of header and in to implementation files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and assignment operator since parent already deletes it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239744 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 19:05:35 +00:00
a1e554d253 [TargetInstrInfo] Add new hook: AnalyzeBranchPredicate.
Summary:
NFC: no one uses AnalyzeBranchPredicate yet.

Add TargetInstrInfo::AnalyzeBranchPredicate and implement for x86.  A
later change adding support for page-fault based implicit null checks
depends on this.

Reviewers: reames, ab, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10200

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239742 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:21 +00:00
319c91bbb0 [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.
Summary:

TargetInstrInfo::getLdStBaseRegImmOfs to
TargetInstrInfo::getMemOpBaseRegImmOfs and implement for x86.  The
implementation only handles a few easy cases now and will be made more
sophisticated in the future.

This is NFCI: the only user of `getLdStBaseRegImmOfs` (now
`getmemOpBaseRegImmOfs`) is `LoadClusterMotion` and `LoadClusterMotion`
is disabled for x86.

Reviewers: reames, ab, MatzeB, atrick

Reviewed By: MatzeB, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239741 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:14 +00:00
1991e2a4df [CodeGen] Introduce a FAULTING_LOAD_OP pseudo-op.
Summary:
This instruction encodes a loading operation that may fault, and a label
to branch to if the load page-faults.  The locations of potentially
faulting loads and their "handler" destinations are recorded in a
FaultMap section, meant to be consumed by LLVM's clients.

Nothing generates FAULTING_LOAD_OP instructions yet, but they will be
used in a future change.

The documentation (FaultMaps.rst) needs improvement and I will update
this diff with a more expanded version shortly.

Depends on D10196

Reviewers: rnk, reames, AndyAyers, ab, atrick, pgavlin

Reviewed By: atrick, pgavlin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10197

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239740 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:08 +00:00
36395e7598 [NFC] Extract X86MCInstLower::LowerMachineOperand.
Summary: Refactoring-only change that will be used later.

Reviewers: reames, atrick

Reviewed By: atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10196

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239739 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 18:44:01 +00:00
2ecc72cc58 On behalf of Alexandros Lamprineas:
LLVM targeting aarch64 doesn't correctly produce aligned accesses for non-aligned
data at -O0/fast-isel (-mno-unaligned-access).
The root cause seems to be in fast-isel not producing unaligned access correctly
for -mno-unaligned-access.

The patch just aborts fast-isel for loads and stores when -mno-unaligned-access is
present. 
The regression test is updated to check this new test case (-mno-unaligned-access 
together with fast-isel).

Differential Revision: http://reviews.llvm.org/D10360



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239732 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 15:48:44 +00:00
ad0b09d10e Revert r239721 - Replace string GNU Triples with llvm::Triple in InitMCObjectFileInfo. NFC.
It appears to cause sparc-little-endian.s to assert on Windows and Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239724 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 10:34:38 +00:00
4a867c7a05 Replace string GNU Triples with llvm::Triple in InitMCObjectFileInfo. NFC.
Summary:
This affects other tools so the previous C++ API has been retained as a
deprecated function for the moment. Clang has been updated with a trivial
patch (not covered by the pre-commit review) to avoid breaking -Werror builds.
Other in-tree tools will be fixed with similar trivial patches.

This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10366



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239721 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 09:19:41 +00:00
5e1ea386d4 [AArch64] Delete two empty files, which should be removed by r239713.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239715 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 02:56:40 +00:00
5ab48a2f69 [AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239713 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 01:56:40 +00:00
6024ab3b8f [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Re-commit after adding "-aarch64-neon-syntax=generic" to fix the failure on OS X.
This patch was firstly committed in r239514, then reverted in r239544 because of a syntax incompatible failure on OS X.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239711 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-15 01:35:49 +00:00
17ae2138b0 AVX-512: Implemented DAG lowering for shuff62x2/shufi62x2 instuctions ( Shuffle Packed Values at 128-bit Granularity )
Tests added , vector-shuffle-512-v8.ll test re-generated.

Differential Revision: http://reviews.llvm.org/D10300

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239697 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 13:07:47 +00:00
3dd555171e Add support for parsing the XOR operator in Intel syntax inline assembly.
Differential Revision: http://reviews.llvm.org/D10385
Patch by marina.yatsina@intel.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239695 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:59:45 +00:00
6ea3ad7e6e AVX-512: Implemented cvtsi2ss/d cvtusi2ss/d instructions with round control for KNL.
Added intrinsics for cvtsi2ss/d instructions.
Added tests for intrinsics and encoding.

Differential Revision: http://reviews.llvm.org/D10430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239694 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-14 12:44:55 +00:00
9223c2cb1e Stripped trailing whitespace. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239672 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 12:51:39 +00:00
bfc6c664fc AMDGPU: s/R600/AMDGPU/ in the Makefiles
Now the library names in the Makefiles match the library names in
LLVMBuild.txt.

This should hopefully fix the remaining bot failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239661 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 05:11:14 +00:00
8ce6c58e41 Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()
r213101 changed the behaviour of this method to not only affect the
PostMachineScheduler scheduler but also the PostRAScheduler scheduler,
renaming should make this fact clear. Also document that the preferred
way is to specify this in the scheduling model instead of overriding
this method.

Differential Revision: http://reviews.llvm.org/D10427

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239659 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:42:16 +00:00
6fee0b00e2 MachineLICM: Use TargetSchedModel instead of just itineraries
This will use Itinieraries if available, but will also work if just a
MCSchedModel is available.

Differential Revision: http://reviews.llvm.org/D10428

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239658 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:42:11 +00:00
953c681473 R600 -> AMDGPU rename
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239657 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-13 03:28:10 +00:00
31b680fa24 AArch64: map bare-metal arm64-macho triple to MachO MC layer.
Far better than an assertion about expecting ELF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239647 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 23:37:11 +00:00
f28da43112 R600/SI: Add assembler support for FLAT instructions
- Add glc, slc, and tfe operands to flat instructions
- Add missing flat instructions
- Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239637 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 20:47:06 +00:00
53aa3e0444 [Hexagon] Making intrinsic tests agnostic to register allocation. Narrowing intrinsic parameters to appropriate width.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239634 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 19:57:32 +00:00
f52f043d3e Wrap some long lines in LLVMBuild files. NFC
As suggested by jroelofs in a prior review (D9752),
it makes sense to generally prefer multi-line format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239632 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 18:44:57 +00:00
3bc62ab179 Remove a hack that tries to align '*'.
The alignment is not required, so we can just remove it for now.

The old code is a hack as it depends on the buffer management to find
the current column.

If the alignment is really desirable, the proper way to do it is
to pass in a formatted_raw_stream that knows the current column.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239603 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-12 12:42:13 +00:00
2bd0221fa4 [WinEH] Put finally pointers in the handler scope table field
We were putting them in the filter field, which is correct for 64-bit
but wrong for 32-bit.

Also switch the order of scope table entry emission so outermost entries
are emitted first, and fix an obvious state assignment bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239574 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 23:37:18 +00:00
d48b38e9ec [Stackmaps][X86] Remove EFLAGS and IP registers from the live-out mask.
Remove the EFLAGS from the stackmap live-out mask. The EFLAGS register is not
supposed to be part of that set, because the X86 calling conventions mark the
register as NOT preserved.

Also remove the IP registers, since spilling and restoring those doesn't really
make any sense.

Related to rdar://problem/21019635.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239568 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 22:40:04 +00:00
3e16bd3aaf [WinEH] Create an llvm.x86.seh.exceptioninfo intrinsic
This intrinsic is like framerecover plus a load. It recovers the EH
registration stack allocation from the parent frame and loads the
exception information field out of it, giving back a pointer to an
EXCEPTION_POINTERS struct. It's designed for clang to use in SEH filter
expressions instead of accessing the EXCEPTION_POINTERS parameter that
is available on x64.

This required a minor change to MC to allow defining a label variable to
another absolute framerecover label variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239567 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 22:32:23 +00:00
4ddb0ced90 Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.
Summary:
For the moment, TargetMachine::getTargetTriple() still returns a StringRef.

This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: ted, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10362

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239554 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 19:41:26 +00:00
fd83cb21ce [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239553 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 19:30:37 +00:00
688e7b3049 This reverts commit r239529 and r239514.
Revert "[AArch64] Match interleaved memory accesses into ldN/stN instructions."
Revert "Fixing MSVC 2013 build error."

The  test/CodeGen/AArch64/aarch64-interleaved-accesses.ll test was failing on OS X.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239544 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 17:30:33 +00:00
f0e3a9c174 Replace string GNU Triples with llvm::Triple in computeDataLayout(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rengolin

Reviewed By: rengolin

Subscribers: llvm-commits, jfb, rengolin

Differential Revision: http://reviews.llvm.org/D10361

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239538 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 15:34:59 +00:00
4bedcbcab3 R600/SI: Define latency for flat instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239535 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 14:51:50 +00:00
a79d4da0f1 R600/SI: Move flat instruction defs to CIInstructions.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239534 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 14:51:49 +00:00
89f93ead2a Fixing MSVC 2013 build error.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239529 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 13:06:02 +00:00
f24e4e46cd Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." (r239396).
Apparently, Arcanist didn't include some of my local changes in my previous
commit attempt.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239523 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 10:36:10 +00:00
9d115effdf [mips][microMIPS] Implement ERET and ERETNC instructions
http://reviews.llvm.org/D10091


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239522 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 10:22:46 +00:00
d09e8beec3 [mips] Change existing uimm10 operand to restrict the accepted immediates
http://reviews.llvm.org/D10312


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239520 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:51:58 +00:00
442f620296 [AArch64] Match interleaved memory accesses into ldN/stN instructions.
Add a pass AArch64InterleavedAccess to identify and match interleaved memory accesses. This pass transforms an interleaved load/store into ldN/stN intrinsic. As Loop Vectorizor disables optimization on interleaved accesses by default, this optimization is also disabled by default. To enable it by "-aarch64-interleaved-access-opt=true"

E.g. Transform an interleaved load (Factor = 2):
       %wide.vec = load <8 x i32>, <8 x i32>* %ptr
       %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>  ; Extract even elements
       %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>  ; Extract odd elements
     Into:
       %ld2 = { <4 x i32>, <4 x i32> } call aarch64.neon.ld2(%ptr)
       %v0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
       %v1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1

E.g. Transform an interleaved store (Factor = 2):
       %i.vec = shuffle %v0, %v1, <0, 4, 1, 5, 2, 6, 3, 7>  ; Interleaved vec
       store <8 x i32> %i.vec, <8 x i32>* %ptr
     Into:
       %v0 = shuffle %i.vec, undef, <0, 1, 2, 3>
       %v1 = shuffle %i.vec, undef, <4, 5, 6, 7>
       call void aarch64.neon.st2(%v0, %v1, %ptr)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239514 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 09:05:02 +00:00
44226ffc19 [X86][SSE] Vectorized i8 and i16 shift operators
This patch ensures that SHL/SRL/SRA shifts for i8 and i16 vectors avoid scalarization. It builds on the existing i8 SHL vectorized implementation of moving the shift bits up to the sign bit position and separating the 4, 2 & 1 bit shifts with several improvements:

1 - SSE41 targets can use (v)pblendvb directly with the sign bit instead of performing a comparison to feed into a VSELECT node.
2 - pre-SSE41 targets were masking + comparing with an 0x80 constant - we avoid this by using the fact that a set sign bit means a negative integer which can be compared against zero to then feed into VSELECT, avoiding the need for a constant mask (zero generation is much cheaper).
3 - SRA i8 needs to be unpacked to the upper byte of a i16 so that the i16 psraw instruction can be correctly used for sign extension - we have to do more work than for SHL/SRL but perf tests indicate that this is still beneficial.

The i16 implementation is similar but simpler than for i8 - we have to do 8, 4, 2 & 1 bit shifts but less shift masking is involved. SSE41 use of (v)pblendvb requires that the i16 shift amount is splatted to both bytes however.

Tested on SSE2, SSE41 and AVX machines.

Differential Revision: http://reviews.llvm.org/D9474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239509 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 07:46:37 +00:00
f7d6501d1d LLVM support for vector quad bit permute and gather instructions through builtins
This patch corresponds to review:
http://reviews.llvm.org/D10096

This is the back end portion of the patch related to D10095.
The patch adds the instructions and back end intrinsics for:
vbpermq
vgbbd


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239505 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 06:21:25 +00:00
7963762fce Revert "Move dllimport name mangling to IR mangler."
This reverts commit r239437.

This broke clang-cl self-hosts. We'd end up calling the __imp_ symbol
directly instead of using it to do an indirect function call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239502 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 01:31:48 +00:00
5a118340dd Remove MachineModuleInfo::UsedFunctions as it has no users.
It hasn't been used since r130964.

This also removes MachineModuleInfo::isUsedFunction and
MachineModuleInfo::AnalyzeModule, both of which were only
there to support UsedFunctions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239501 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-11 01:04:56 +00:00
e0d6eef952 change assert that will never fire to llvm_unreachable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239497 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 23:27:33 +00:00
c826b54b52 [x86] Add a reassociation optimization to increase ILP via the MachineCombiner pass
This is a reimplementation of D9780 at the machine instruction level rather than the DAG.

Use the MachineCombiner pass to reassociate scalar single-precision AVX additions (just a
starting point; see the TODO comments) to increase ILP when it's safe to do so.

The code is closely based on the existing MachineCombiner optimization that is implemented
for AArch64.

This patch should not cause the kind of spilling tragedy that led to the reversion of r236031.

Differential Revision: http://reviews.llvm.org/D10321



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239486 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 20:32:21 +00:00
c196bfecd6 [Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239477 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 16:52:32 +00:00
d5254aba82 [Hexagon] Make global arrays 'static const'. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239475 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 14:43:59 +00:00
4d13f315d1 Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.
Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: rafael

Reviewed By: rafael

Subscribers: rafael, ted, jfb, llvm-commits, rengolin, jholewinski

Differential Revision: http://reviews.llvm.org/D10311


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239467 91177308-0d34-0410-b5e6-96231b3b80d8
2015-06-10 12:11:26 +00:00