84 Commits

Author SHA1 Message Date
Matt Arsenault
30eac4b85a AMDGPU: Fix v16i32 to v16i8 truncstore
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243731 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 04:12:04 +00:00
Matt Arsenault
01e2215a94 AMDGPU/SI: Set DwarfRegNum
This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243723 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:12:10 +00:00
Tom Stellard
b0619e0be3 AMDGPU/SI: Remove unused pattern for f32 constant loads
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11603

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243719 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-31 01:02:32 +00:00
Matt Arsenault
ece90bb19e AMDGPU: Set SubRegIndex size and offset
I'm not sure what reasons the comment here could have
had for not setting these. Without these set, there is
an assertion hit during DWARF emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243661 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:03:11 +00:00
Matt Arsenault
b240003d58 AMDGPU: Fix unreachable when emitting binary debug info
Copy implementation of applyFixup from AArch64 with AArch64 bits
ripped out.

Tests will be included with a later commit. Several other
problems must be fixed before binary debug info emission
will work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243660 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 17:03:08 +00:00
Tom Stellard
a495784ea0 AMDGPU/SI: Simplify moveSMRDToVALU()
Summary:
Replace the switch on instruction opcode with a switch on register size.
This way we don't need to update the switch statement when we add new
SMRD variants.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243652 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:20:42 +00:00
Tom Stellard
a3a8dc4c30 AMDGPU/SI: Remove isTriviallyReMaterializable() function from SIInstrInfo
Summary:
This function is never called.  isReallyTriviallyReMaterializable() is
the function that should be implemented instead.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11620

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243651 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-30 16:20:40 +00:00
Nick Lewycky
6fc1adf9c7 Fix typo "fuction" noticed in comments in AssumptionCache.h, and also all the other files that have the same typo. All comments, no functionality change! (Merely a "fuctionality" change.)
Bonus change to remove emacs major mode marker from SystemZMachineFunctionInfo.cpp because emacs already knows it's C++ from the extension. Also fix typo "appeary" in AMDGPUMCAsmInfo.h.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243585 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-29 22:32:47 +00:00
Alex Lorenz
a27dfaf544 Fix broken ArrayRef conversion from r243497.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243501 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 23:34:27 +00:00
Alex Lorenz
ba90cee0f1 MIR Serialization: Serialize the target index machine operands.
Reviewers: Duncan P. N. Exon Smith


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243497 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 23:02:45 +00:00
Matt Arsenault
03b49c843a AMDGPU: Don't try to use LDS/vector for private if pointer value stored
If the pointer is the store's value operand, this would produce
a broken module. Make sure the use is actually for the pointer operand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243462 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 18:47:00 +00:00
Matt Arsenault
7a1c02d1f7 AMDGPU: Fix crash if called function is a bitcast
getCalledFunction() is null, so this would crash. Replace
crash with an error on unsupported call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243461 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 18:29:14 +00:00
Matt Arsenault
c3f2d5b690 AMDGPU: Fix return type of getImplicitParameterOffset.
Patch by Zoltan Gilian <zoltan.gilian@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243459 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-28 18:09:55 +00:00
Colin LeMahieu
f78e199cb2 [llvm-mc] Pushing plumbing through for --fatal-warnings flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243334 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 21:56:53 +00:00
Marek Olsak
dbd8d4f056 AMDGPU: don't match vgpr loads for constant loads
Author: Dave Airlie <airlied@redhat.com>

In order to implement indirect sampler loads, we don't
want to match on a VGPR load but an SGPR one for constants,
as we cannot feed VGPRs to the sampler only SGPRs.

this should be applicable for llvm 3.7 as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243294 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 18:16:08 +00:00
Marek Olsak
bf26b3fcae AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaround
This is a candidate for 3.7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243263 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-27 11:37:42 +00:00
Chandler Carruth
f020cb2f75 [PM/AA] Remove all of the dead AliasAnalysis pointers being threaded
through APIs that are no longer necessary now that the update API has
been removed.

This will make changes to the AA interfaces significantly less
disruptive (I hope). Either way, it seems like a really nice cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242882 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-22 09:52:54 +00:00
Matt Arsenault
1cd0962919 AMDGPU: Set isMoveImm on s_movk_i32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242747 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-21 00:40:08 +00:00
Tom Stellard
f799b25cfc AMDGPU/SI: Add VI patterns to select FLAT instructions for global memory ops
Summary:
The MUBUF addr64 bit has been removed on VI, so we must use FLAT
instructions when the pointer is stored in VGPRs.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11067

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242673 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-20 14:28:41 +00:00
Simon Pilgrim
c365e7e2b5 Remove TargetInstrInfo::canFoldMemoryOperand
canFoldMemoryOperand is not actually used anywhere in the codebase - all existing users instead call foldMemoryOperand directly when they wish to fold and can correctly deduce what they need from the return value. 

This patch removes the canFoldMemoryOperand base function and the target implementations; only x86 had a real (bit-rotted) implementation, although AMDGPU had a preparatory stub that had never needed to be completed.

Differential Revision: http://reviews.llvm.org/D11331

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242638 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-19 10:50:53 +00:00
Tom Stellard
104dab3e04 AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11226

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242434 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 19:40:09 +00:00
Tom Stellard
cac05d9b58 AMDPGU/SI: Use AssertZext node to mask high bit for scratch offsets
Summary:
We can safely assume that the high bit of scratch offsets will never
be set, because this would require at least 128 GB of GPU memory.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11225

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242433 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 19:40:07 +00:00
Tom Stellard
2da44c31e3 AMDGPU/R600: Remove unused variable
This fixes a warning introduced by r242410.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242412 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 16:13:34 +00:00
Tom Stellard
2f8588b7a7 AMDPGU/R600: Replace llvm_unreachable() call with LLVMContext::emitError()
Summary:
This fixes an issue on MIPS where the infinite-loop-evergreen.ll test
was failing to terminate.

Fixes PR24147.

Reviewers: arsenm, dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11260

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242410 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 15:38:29 +00:00
Mehdi Amini
e03f4bd255 Add missing break in switch case in R600ISelLowering
Summary: Catched by coverity.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11120

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242388 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-16 06:23:12 +00:00
Pete Cooper
ba77f37392 Add allnodes() iterator range to SelectionDAG. NFC.
SelectionDAG already had begin/end methods for iterating over all
the nodes, but didn't define an iterator_range for us in foreach
loops.

This adds such a method and uses it in some of the eligible places
throughout the backends.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242212 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 22:10:54 +00:00
Matt Arsenault
ba38e6c2ae AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)
This can be done only with moves which theoretically
will optimize better later.

Although this transform increases the instruction count,
it should be code size / cycle count neutral in the worst
VALU case. It also seems to slightly improve a couple
of testcases due to other DAG combines this exposes.

This is probably slightly worse for the SALU case, so
it might be better to handle this during moveToVALU,
although then you lose some simplifications like
the load width reducing in the simple testcase.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242177 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 18:20:33 +00:00
Matt Arsenault
3aa0d7cb53 AMDGPU/SI: Fix read2 merging into a super register.
If the read2 produced was supposed to be writing into a
super register, it would use the wrong subregister indices.
Fix this by inserting copies, so we only ever write to a vreg_64.
Run the register coalescer again to clean this up, although this
isn't ideal and often does result in an extra move.

Also remove the assert that offset1 > offset0.

There isn't a real reason to not allow this other than a minor
convenience in the compiler, and it doesn't seem worth the effort
of avoiding it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242174 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 17:57:36 +00:00
Matthias Braun
2addf067a2 MachineRegisterInfo: Remove UsedPhysReg infrastructure
We have a detailed def/use lists for every physical register in
MachineRegisterInfo anyway, so there is little use in maintaining an
additional bitset of which ones are used.

Removing it frees us from extra book keeping. This simplifies
VirtRegMap.

Differential Revision: http://reviews.llvm.org/D10911

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242173 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 17:52:07 +00:00
Tom Stellard
adb194b458 AMDGPU/SI: Add support for shrinking v_cndmask_b32_e32 instructions
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242146 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-14 14:15:03 +00:00
Matt Arsenault
bae3cf3a1b AMDGPU: Minor cleanups to always inline pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242053 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 19:08:36 +00:00
Tom Stellard
f5be357d37 AMDGPU/SI: Select mad patterns to v_mac_f32
The two-address instruction pass will convert these back to v_mad_f32
if necessary.

Differential Revision: http://reviews.llvm.org/D11060

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242038 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-13 15:47:57 +00:00
Matt Arsenault
ce43851064 AMDGPU: Fix chains for memory ops dependent on argument loads
Most loads and stores are derived from pointers derived from
a kernel argument load inserted during argument lowering.
This was just using the EntryToken chain for the argument loads,
and any users of these loads were also on the EntryToken chain.

Return the chain of the lowered argument load so that dependent loads
end up on the correct chain.

No test since I'm not aware of any case where this actually
broke.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241960 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:51:36 +00:00
Duncan P. N. Exon Smith
16859aa242 MC: Remove MCSubtargetInfo() default constructor
Force all creators of `MCSubtargetInfo` to immediately initialize it,
merging the default constructor and the initializer into an initializing
constructor.  Besides cleaning up the code a little, this makes it clear
that the initializer is never called again later.

Out-of-tree backends need a trivial change: instead of calling:

    auto *X = new MCSubtargetInfo();
    InitXYZMCSubtargetInfo(X, ...);
    return X;

they should call:

    return createXYZMCSubtargetInfoImpl(...);

There's no real functionality change here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241957 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:43:42 +00:00
Matt Arsenault
bd884766bf AMDGPU: Use requested chain when lowering arguments
No test since I'm not aware of any case where this will
end up being a different chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241954 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-10 22:28:41 +00:00
Tom Stellard
847c023a2e AMDGPU: Add helper function for implicit parameter offsets.
Patch by: Zoltan Gilian

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241861 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 21:20:37 +00:00
Matt Arsenault
0685a5c5ed AMDGPU/R600: Return correct chain when lowering loads
The other LowerLOAD should be returning the correct chain.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241839 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 18:47:03 +00:00
Tom Stellard
2b2d86178c AMDGPU/SI: The SIShrinkInstructions pass should only fold immediates with one use
This is convered by existing testcases and will be exposed by a future
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:36 +00:00
Tom Stellard
e05910e677 AMDGPU/SI: Fix crash on physical registers in SIInstrInfo::isOperandLegal()
No test case for this.  I ran into it while working on some improvements
to SIShrinkInstructions.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241816 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 16:30:27 +00:00
Mehdi Amini
cdc323b2b7 Re-instate the EVT parameter to getScalarShiftAmountTy() for OOT user
A documentation for this function would be nice by the way.

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241807 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 15:12:23 +00:00
Mehdi Amini
691b2ff11e Remove getDataLayout() from TargetLowering
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: yaron.keren, rafael, llvm-commits, jholewinski

Differential Revision: http://reviews.llvm.org/D11042

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241779 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:52 +00:00
Mehdi Amini
0e496c884c Make isLegalAddressingMode() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11040

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:40 +00:00
Mehdi Amini
29a2d864d4 Make TargetLowering::getShiftAmountTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11037

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241776 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:20 +00:00
Mehdi Amini
f29cc18dcb Make TargetLowering::getPointerTy() taking DataLayout as an argument
Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, ted, yaron.keren, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D11028

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241775 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:09:04 +00:00
Mehdi Amini
966e6ca1ac Make TargetTransformInfo keeping a reference to the Module DataLayout
DataLayout is no longer optional. It was initialized with or without
a DataLayout, and the DataLayout when supplied could have been the
one from the TargetMachine.

Summary:
This change is part of a series of commits dedicated to have a single
DataLayout during compilation by using always the one owned by the
module.

Reviewers: echristo

Subscribers: jholewinski, llvm-commits, rafael, yaron.keren

Differential Revision: http://reviews.llvm.org/D11021

From: Mehdi Amini <mehdi.amini@apple.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241774 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-09 02:08:42 +00:00
Matt Arsenault
b560f9ca2f AMDGPU: Run SIInsertWaits as pre-emit pass
Running this after the scheduler enables scheduling
waits later so other ALU instructions can run while
this would be waiting.

When combined with enabling the post-RA scheduler, this
gives about a ~20% improvement on sgemm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241473 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 17:02:20 +00:00
Daniel Sanders
96fe9196e9 Change the last few internal StringRef triples into Triple objects.
Summary:
This concludes the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

At this point, the StringRef-form of GNU Triples should only be used in the
public API (including IR serialization) and a couple objects that directly
interact with the API (most notably the Module class). The next step is to
replace these Triple objects with the TargetTuple object that will represent
our authoratative/unambiguous internal equivalent to GNU Triples.

Reviewers: rengolin

Subscribers: llvm-commits, jholewinski, ted, rengolin

Differential Revision: http://reviews.llvm.org/D10962

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241472 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:56:07 +00:00
Matt Arsenault
6fe7acaaf8 AMDGPU/SI: Add debugging subtarget feature for DS offsets
We don't have a good way to detect most situations where
DS offsets are usable on SI, so add an option to force using
them even if unsafe for debugging performance problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241462 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-06 16:01:58 +00:00
Benjamin Kramer
54b3b4c15e [TargetLowering] StringRefize asm constraint getters.
There is some functional change here because it changes target code from
atoi(3) to StringRef::getAsInteger which has error checking. For valid
constraints there should be no difference.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241411 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-05 19:29:18 +00:00
Matt Arsenault
11528555b1 AMDGPU: Fix indentation of switch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241380 91177308-0d34-0410-b5e6-96231b3b80d8
2015-07-03 23:33:38 +00:00