6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-23 20:29:30 +00:00
Code Issues Projects Releases Wiki Activity
79,178 Commits 39 Branches 0 Tags
Commit Graph

446 Commits

Author SHA1 Message Date
Jim Grosbach
f7c66fa0de ARM NEON mnemonic aliase for vrecpeq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147109 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:52:37 +00:00
Jim Grosbach
5f669fa8ba ARM NEON optional data type on VSWP instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147103 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:09:28 +00:00
Jim Grosbach
4553fa3128 ARM NEON mnemonic aliases for vzipq and vswpq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147102 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 23:04:33 +00:00
Jim Grosbach
e6949b1399 ARM NEON assmebly parsing for VLD2 to all lanes instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 19:40:55 +00:00
Jim Grosbach
3471d4fbbd ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-21 00:38:54 +00:00
Jim Grosbach
5b484312c6 ARM assembly parsing and encoding for VST2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 20:46:29 +00:00
Jim Grosbach
95fad1c603 ARM assembly parsing and encoding for VLD2 single-element, double spaced. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-20 19:21:26 +00:00
Jim Grosbach
9b0878512f ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates. 
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"

rdar://10603913

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146925 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 23:51:07 +00:00
Jim Grosbach
d22170e16a ARM NEON two-operand aliases for VPADD. 
rdar://10602276

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 19:51:03 +00:00
Jim Grosbach
61b74b4247 ARM NEON implied destination aliases for VMAX/VMIN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:57:38 +00:00
Jim Grosbach
eeaf1c1636 ARM NEON relax parse time diagnostics for alignment specifiers. 
There's more variation that we need to handle. Error checking will need
to be on operand predicates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:31:43 +00:00
Jim Grosbach
3346dcef02 Tidy up. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-19 18:11:17 +00:00
Jim Grosbach
ddecfe54a3 ARM NEON aliases for vmovq.f* 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146714 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-16 00:12:22 +00:00
Jim Grosbach
a738da7bd3 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:56:33 +00:00
Jim Grosbach
60d99a5278 ARM NEON VTBL/VTBX assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-15 22:27:11 +00:00
Jim Grosbach
799ca9d1b7 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146608 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:35:06 +00:00
Jim Grosbach
9b1b390288 ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 23:25:46 +00:00
Jim Grosbach
ec04a3f8db ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:49:24 +00:00
Jim Grosbach
2dbab5c33d Nuke old code. Missed in last commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146590 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:41:32 +00:00
Jim Grosbach
bb3a2e4d0d ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 21:32:11 +00:00
Jim Grosbach
20accfc6c7 ARM NEON improve factoring a bit. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146585 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 20:59:15 +00:00
Jim Grosbach
e90ac9bce9 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-14 19:35:22 +00:00
Jim Grosbach
0f293de207 ARM NEON two-operand aliases for VQDMULH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:40:37 +00:00
Jim Grosbach
485d8bf7e5 ARM add more 'gas' compatibility aliases for NEON instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146507 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-13 20:08:32 +00:00
Jim Grosbach
21d7fb814a ARM add some pre-UAL VFP mnemonics for convenience when porting old code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146296 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 23:34:09 +00:00
Jim Grosbach
4332983e77 ARM NEON data type aliases for VBIC(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146281 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 21:46:04 +00:00
Jim Grosbach
a4e3c7fc4b ARM assembly parsing and encoding for VLD2 with writeback. 
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.

Add tests for the instruction variants now supported.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 21:28:25 +00:00
Jim Grosbach
2af50d981d Tidy up. Better base class factoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 19:07:20 +00:00
Jim Grosbach
1f94ec7b59 Tidy up. Better base class factoring. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146266 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-09 18:54:11 +00:00
Jim Grosbach
8759c3f548 ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:19:04 +00:00
Jim Grosbach
6b044c2609 ARM VSHR implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 22:06:06 +00:00
Jim Grosbach
120313435d ARM VSUB implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:56:26 +00:00
Jim Grosbach
9e7b42a40e ARM VQADD implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:49:43 +00:00
Jim Grosbach
1c2c8a9389 ARM a few more VMUL implied destination operand form aliases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 20:42:35 +00:00
Jim Grosbach
730fe6c1b6 ARM NEON two-operand aliases for VSHL(immediate). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:30:04 +00:00
Jim Grosbach
ff4cbb4c9a ARM NEON two-operand aliases for VSHL(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:12:35 +00:00
Jim Grosbach
517a013a4f Fix copy/past-o. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146120 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 01:02:26 +00:00
Jim Grosbach
2b8810c500 ARM NEON two-operand aliases for VMUL. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146119 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:59:47 +00:00
Jim Grosbach
a44f2c4a28 ARM optional destination operand variants for VEXT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-08 00:43:47 +00:00
Jim Grosbach
9fa0a743e6 ARM two-operand aliases for VAND/VEOR/VORR instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:08:12 +00:00
Jim Grosbach
30a264eb7f ARM two-operand aliases for VADDW instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 23:01:10 +00:00
Jim Grosbach
d900441e13 ARM two-operand aliases for VADD instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 22:52:54 +00:00
Jim Grosbach
470855b24f ARM NEON VCLT(register) is a pseudo aliasing VCGT(register). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 17:51:15 +00:00
Jim Grosbach
1ceef1a491 ARM tidy up and remove no longer needed InstAlias definitions. 
The TokenAlias handling of data type suffices renders these unnecessary.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146010 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:50:36 +00:00
Jim Grosbach
3b8991cc98 ARM: NEON SHLL instruction immediate operand range checking. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146003 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 01:07:24 +00:00
Jim Grosbach
4e4139588c ARM: Parameterize the immediate operand type for NEON VSHLL. 
No functional change yet. Will be implementing range-checked immediates
for better diagnostics and disambiguation of instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145994 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-07 00:02:17 +00:00
Jim Grosbach
253ef7a779 ARM assembly parsing for the rest of the VMUL data type aliases. 
Finish up rdar://10522016.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:29:59 +00:00
Jim Grosbach
422faab909 Fix previous commit. Oops. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145844 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:12:26 +00:00
Jim Grosbach
45755a77ec Tidy up. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145843 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 20:09:44 +00:00
Jim Grosbach
afb500ace1 ARM assmebler parsing for two-operand VMUL instructions. 
Combined destination and first source operand for f32 variant of the VMUL
(by scalar) instruction.

rdar://10522016

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145842 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-12-05 19:55:46 +00:00