Make all of the RecTy constructors private, and use get() factory
methods instead. Return singleton instances when it makes sense.
ListTy instance pointers are stored in the element RecTy instance.
BitsRecTy instance pointers, one per length, are stored in a static vector.
Also unique DefInit instances. A Record has a unique DefInit which
has a unique RecordRecTy instance.
This saves some 200k-300k RecTy allocations when parsing ARM.td. It
reduces TableGen's heap usage by almost 50%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135399 91177308-0d34-0410-b5e6-96231b3b80d8
Manage Inits in a FoldingSet. This provides several benefits:
- Memory for Inits is properly managed
- Duplicate Inits are folded into Flyweights, saving memory
- It enforces const-correctness, protecting against certain classes
of bugs
The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen. This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134907 91177308-0d34-0410-b5e6-96231b3b80d8
class A<bit a, bits<3> x, bits<3> y> {
bits<3> z;
let z = !if(a, x, y);
}
The variable z will get the value of x when 'a' is 1 and 'y' when a is '0'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121666 91177308-0d34-0410-b5e6-96231b3b80d8
Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117862 91177308-0d34-0410-b5e6-96231b3b80d8
as the operator of the dag. Specifically, this allows parsing things
like (F.x 4) in addition to just (a 4).
Unfortunately, this runs afoul of an idiom being used by llvmc. It
is using dags like (foo [1,2,3]) to represent a list of stuff being
passed into foo. With this change, this is parsed as a [1,2,3]
subscript on foo instead of being the first argument to the dag.
Cope with this in the short term by requiring a "-llvmc-temp-hack"
argument to tblgen to get the old parsing behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115742 91177308-0d34-0410-b5e6-96231b3b80d8
other operators. For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73078 91177308-0d34-0410-b5e6-96231b3b80d8
Use it on dags and lists like this:
class decls {
string name;
}
def Decls : decls;
class B<list<string> names> : A<!foreach(Decls.name, names, !strconcat(Decls.name, ", Sr."))>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71803 91177308-0d34-0410-b5e6-96231b3b80d8
Create an OpInit class to serve as a base for all operation Inits.
Move parsing of operation constructs to separate functions and reference
from multiple places.
Add some commented out new operations. Coming soon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71789 91177308-0d34-0410-b5e6-96231b3b80d8
#NAME# with the name of the defm instantiating the multiclass. This is
useful for AVX instruction naming where a "V" prefix is standard
throughout the ISA. For example:
multiclass SSE_AVX_Inst<...> {
def SS : Instr<...>;
def SD : Instr<...>;
def PS : Instr<...>;
def PD : Instr<...>;
def V#NAME#SS : Instr<...>;
def V#NAME#SD : Instr<...>;
def V#NAME#PS : Instr<...>;
def V#NAME#PD : Instr<...>;
}
defm ADD : SSE_AVX_Inst<...>;
Results in
ADDSS
ADDSD
ADDPS
ADDPD
VADDSS
VADDSD
VADDPS
VADDPD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70979 91177308-0d34-0410-b5e6-96231b3b80d8
so that it doesn't shadow the instance variable of the same name.
Make the parameter names in method declarations match the definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70502 91177308-0d34-0410-b5e6-96231b3b80d8
by base multiclasses. Do not attempt to alter defs from previous base
multiclasses. This fixes multiple multiclass inheritance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69974 91177308-0d34-0410-b5e6-96231b3b80d8
in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite,
and as it turns out, cleans up a hack in the Alpha instruction info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8
