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78 Commits

Author SHA1 Message Date
Colin LeMahieu
5de3458c18 [Hexagon] Adding asrh instruction, removing unused multiclasses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 18:04:42 +00:00
Colin LeMahieu
c1c7be0928 [Hexagon] Adding aslh instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222668 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 17:44:19 +00:00
Colin LeMahieu
f309d8ee65 [Hexagon] Adding zxth instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222662 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 17:11:34 +00:00
Colin LeMahieu
a723df08bb [Hexagon] Adding zxtb instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-24 16:48:43 +00:00
Colin LeMahieu
88109da602 [Hexagon] Adding sxth instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222577 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-21 21:54:59 +00:00
Colin LeMahieu
326816c88f [Hexagon] Adding sxtb instruction. Renaming some identically named classes that will be removed after converting referencing defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222575 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-21 21:35:52 +00:00
Colin LeMahieu
a3b0670792 [Hexagon] Removing SUB_rr and replacing with A2_sub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222571 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-21 21:19:18 +00:00
Colin LeMahieu
e8cdd171f9 [Hexagon] Adding A2_xor instruction with IR selection pattern and test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222399 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 23:22:23 +00:00
Colin LeMahieu
fb1c650fd0 [Hexagon] Adding A2_or instruction with IR selection pattern and test. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222396 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-19 22:58:04 +00:00
Colin LeMahieu
642bb08576 [Hexagon] Adding A2_and instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222274 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-18 22:45:47 +00:00
Colin LeMahieu
ed37b1e2d0 [Hexagon] Adding A2_sub instruction 
Renaming test files.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222263 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-18 21:51:51 +00:00
Colin LeMahieu
b7927f100d [Hexagon] Converting from ADD_rr to A2_add which has encoding bits. 
Adding test to show correct instruction selection and encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222249 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-18 20:28:11 +00:00
Colin LeMahieu
38d3e4d5d8 [Hexagon] Reverting 220584 to address ASAN errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221210 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-04 00:14:36 +00:00
Colin LeMahieu
8699f5390b [Hexagon] Resubmission of 220427 
Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.
Adding encoding bits for add opcode.
Adding llvm-mc tests.
Removing unit tests.

http://reviews.llvm.org/D5624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220584 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-24 19:00:32 +00:00
NAKAMURA Takumi
effe629b3d Revert r220427, "[Hexagon] Adding encoding bits for add opcode." 
It brought cyclic dependecy between HexagonAsmPrinter and HexagonDesc.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220478 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-23 11:31:22 +00:00
Colin LeMahieu
545127f54d [Hexagon] Adding encoding bits for add opcode. 
Adding llvm-mc tests.
Removing unit tests.

http://reviews.llvm.org/D5624

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220427 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-22 20:58:35 +00:00
Colin LeMahieu
324cd41b60 [Hexagon] Adding basic disassembler. 
Marking all instructions as CodeGenOnly since encoding bits are not set yet.
http://reviews.llvm.org/D5829?vs=on&id=15023&whitespace=ignore-all#toc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220393 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-22 16:49:14 +00:00
Jyotsna Verma
8b915bad69 [Hexagon] Add New TSFlags to be used in the upcoming patches. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208239 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-07 19:07:34 +00:00
Jyotsna Verma
a29a8965e2 Hexagon: Pass to replace tranfer/copy instructions into combine instruction 
where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181817 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-14 18:54:06 +00:00
Jyotsna Verma
8cc93593cd Hexagon: Set accessSize and addrMode on all load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-07 15:06:29 +00:00
Pranav Bhandarkar
02d937d864 Hexagon - Add peephole optimizations for zero extends. 
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 20:22:51 +00:00
Jyotsna Verma
6ea706e40e Hexagon: Use multiclass for Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 21:37:34 +00:00
Jyotsna Verma
42ba77db53 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:17:40 +00:00
Jyotsna Verma
47089c91ae Hexagon: Remove assembler mapped instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 19:15:55 +00:00
Jyotsna Verma
1877dc00e7 Hexagon: Set isPredicatedNew flag on predicate new instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 18:01:06 +00:00
Jyotsna Verma
c1406d76ec Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 17:46:52 +00:00
Jyotsna Verma
810848d5b3 Hexagon: Replace switch-case in isDotNewInst with TSFlags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 19:44:04 +00:00
Jyotsna Verma
4f2ef94d6a Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 16:25:57 +00:00
Jyotsna Verma
7bb9585c6e Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:43:57 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 14:15:15 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 19:10:28 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:37:46 +00:00
Jyotsna Verma
ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions. 
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:42:28 +00:00
Jyotsna Verma
84a2c2bbb5 Hexagon: Change insn class to support instruction encoding. 
This patch doesn't introduce any functionality changes.
It adds some new fields to the Hexagon instruction classes and
changes their layout to support instruction encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-14 19:57:17 +00:00
Jakob Stoklund Olesen
87b87ad8fb Move MRI liveouts to Hexagon return instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174407 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-05 18:08:43 +00:00
Jyotsna Verma
3e1635d08c Hexagon: Add V4 combine instructions and some more Def Pats for V2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-04 15:52:56 +00:00
Jyotsna Verma
9c3846c99c Use multiclass for post-increment store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 18:42:41 +00:00
Jyotsna Verma
30c3bbe007 Add constant extender support for MInst type instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173813 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-29 18:18:50 +00:00
Craig Topper
a812641879 Remove more unnecessary # operators with nothing to paste proceeding them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171702 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 06:14:20 +00:00
Craig Topper
71ab7a79a7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-01-07 05:45:56 +00:00
Jyotsna Verma
82a36e2b59 Add constant extender support to GP-relative load/store instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170672 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 06:52:46 +00:00
Jyotsna Verma
4b3aafb4b2 Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count trailing/leading zeros) 
instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169287 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 18:05:01 +00:00
Jyotsna Verma
9ee1ec6115 Add constant extender support to ALU32 instructions for V2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169284 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 17:12:00 +00:00
Jyotsna Verma
3db6676e32 Move all operand definitions into HexagonOperands.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169213 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 05:00:31 +00:00
Jyotsna Verma
3e91da24bc Move generic Hexagon subtarget information into Hexagon.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169212 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-04 04:29:16 +00:00
Jyotsna Verma
bfeecc1306 Define store instructions with base+immediate offset addressing mode 
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169168 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-03 22:26:28 +00:00
Jyotsna Verma
b434a8130f Define load instructions with base+immediate offset addressing mode 
using multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169153 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-03 21:13:13 +00:00
Jyotsna Verma
f432be0c62 Use multiclass for the load instructions with MEMri operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169018 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-30 17:31:52 +00:00
Jyotsna Verma
b76c710aab Use multiclass for the store instructions with MEMri operand. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-11-30 06:10:22 +00:00