Commit Graph

21835 Commits

Author SHA1 Message Date
Simon Atanasyan
c5e99819f4 [Mips] Adjust float ABI settings in case of MIPS16 mode.
Hard float for mips16 means essentially to compile as soft float but to
use a runtime library for soft float that is written with native mips32
floating point instructions (those runtime routines run in mips32 hard
float mode).

The patch reviewed by Reed Kotler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 12:20:17 +00:00
Chandler Carruth
ed1951e79f Fix an issue where SROA computed different results based on the relative
order of slices of the alloca which have exactly the same size and other
properties. This was found by a perniciously unstable sort
implementation used to flush out buggy uses of the algorithm.

The fundamental idea is that findCommonType should return the best
common type it can find across all of the slices in the range. There
were two bugs here previously:

1) We would accept an integer type smaller than a byte-width multiple,
   and if there were different bit-width integer types, we would accept
   the first one. This caused an actual failure in the testcase updated
   here when the sort order changed.
2) If we found a bad combination of types or a non-load, non-store use
   before an integer typed load or store we would bail, but if we found
   the integere typed load or store, we would use it. The correct
   behavior is to always use an integer typed operation which covers the
   partition if one exists.

While a clever debugging sort algorithm found problem #1 in our existing
test cases, I have no useful test case ideas for #2. I spotted in by
inspection when looking at this code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 09:03:18 +00:00
Daniel Jasper
f5afe719df Add .clang-format without column limit to subdirectory tests/.
A column limit in the test folder can lead to trouble as the RUN, CHECK,
etc. comments can potentially be broken over multiple lines changing
their meaning. Without column limit, clang-format will simply keep the
test author's line breaks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195100 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 04:26:05 +00:00
Andrew Trick
d73d4f4ef2 Use symbolic operands in the patchpoint folding routine and fix a spilling bug.
Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 03:29:59 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 02:17:05 +00:00
Jiangning Liu
f11b55c5cc Implement AArch64 SISD intrinsics for vget_high and vget_low.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195074 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:46:48 +00:00
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:40:25 +00:00
Jiangning Liu
01dd5728cc Add predicate for AArch64 crypto instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:38:31 +00:00
Jack Carter
e53969b475 [Mips] Support for MicroMips STO refactoring.
No true functional changes.

Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.

Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.

XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 01:25:18 +00:00
David Blaikie
26efdc5621 llvm-dwarfdump: support for emitting only the debug_types section using -debug-dump
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195063 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-19 00:29:42 +00:00
Reid Kleckner
a7b7a7d629 Revert "COFF: Emit all MCSymbols rather than filtering out some of them"
This reverts commit r190888, to fix PR17967.  The original change wasn't
the right way to get @feat.00 into the object file.  The right fix is to
make @feat.00 be a global symbol.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:08:12 +00:00
Adrian Prantl
940267e7f2 Debug info: Let LowerDbgDeclare perfom the dbg.declare -> dbg.value
lowering only for load/stores to scalar allocas. The resulting values
confuse the backend and don't add anything because we can describe
array-allocas with a dbg.declare intrinsic just fine.

rdar://problem/15464571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195052 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 23:04:38 +00:00
Paul Robinson
fe45fd084d The 'optnone' attribute means don't inline anything into this function
(except functions marked always_inline).
Functions with 'optnone' must also have 'noinline' so they don't get
inlined into any other function.

Based on work by Andrea Di Biagio.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195046 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 21:44:03 +00:00
Matt Arsenault
3560dd2dcd R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:55 +00:00
Matt Arsenault
9bc4b2c0da R600/SI: Fix multiple SGPR reads when using VCC.
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:50 +00:00
Matt Arsenault
e64a289609 R600/SI: Implement add i64, but do not yet enable.
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:47 +00:00
Matt Arsenault
3e38856f04 R600/SI: Move patterns to match add / sub to scalar instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 20:09:29 +00:00
Tom Stellard
b570599c8f R600: Enable the IR structurizer by default
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195031 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:44 +00:00
Tom Stellard
44248e0f63 R600: Fix a crash in the AMDILCFGStrucurizer
The ifPatternMatch() function was not correctly reporting the number
of matches in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195030 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 19:43:38 +00:00
Tom Stellard
204c953cd5 R600/SI: Fix illegal VGPR->SGPR copy inside of loop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195026 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 18:50:20 +00:00
Tom Stellard
bf9ddd5e8f R600/SI: Fix another case of illegal VGPR->SGPR copy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195025 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 18:50:15 +00:00
Alexey Samsonov
64409ad8e3 [ASan] Fix PR17867 - make sure ASan doesn't crash if use-after-scope and use-after-return are combined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195014 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 14:53:55 +00:00
NAKAMURA Takumi
874081c8fa [PR17978] Mark two ARM/fast-isel tests as XFAIL:vg_leak due to GV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195010 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:50:19 +00:00
Arnold Schwaighofer
07a3c481c6 LoopVectorizer: Extend the induction variable to a larger type
In some case the loop exit count computation can overflow. Extend the type to
prevent most of those cases.

The problem is loops like:
int main ()
{
  int a = 1;
  char b = 0;
  lbl:
    a &= 4;
    b--;
    if (b) goto lbl;
  return a;
}

The backedge count is 255. The induction variable type is i8. If we add one to
255 to get the exit count we overflow to zero.

To work around this issue we extend the type of the induction variable to i32 in
the case of i8 and i16.

PR17532

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195008 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:14:32 +00:00
Daniel Sanders
23427207ea [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code for (ConstantFP 0.0)
Fixed an inappropriate use of BuildPairF64 when compiling for MIPS32 with FP64
which resulted in an impossible constraint on the register allocation. It now
uses BuildPairF64_64.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195007 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:12:43 +00:00
Matheus Almeida
26651c7a66 [mips][msa] Update encoding of bnz.v (typo).
Note that there's no hardware yet that relies on that encoding.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195006 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 13:09:54 +00:00
Matheus Almeida
95adf91f29 [mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded.
The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 12:32:49 +00:00
Kevin Qin
69b2447b6a [AArch64 NEON]Add mov alias for simd copy instructions.
Set some unspecified bits of INS/DUP to zero as ARMARM requested.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194996 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 09:20:32 +00:00
Hao Liu
97577757c6 Implement the newly added ACLE functions for ld1/st1 with 2/3/4 vectors.
The functions are like: vst1_s8_x2 ...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194990 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-18 06:31:53 +00:00
Bill Wendling
281e8eb9fd Testcase for PR17964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194961 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-17 10:53:19 +00:00
Benjamin Kramer
d5ae5b0186 DAGCombiner: Partially revert r192795, getNOT was fixed not to create illegal constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194959 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-17 10:40:03 +00:00
Hal Finkel
390564206f Add the cold attribute to error-reporting call sites
Generally speaking, control flow paths with error reporting calls are cold.
So far, error reporting calls are calls to perror and calls to fprintf,
fwrite, etc. with stderr as the stream. This can be extended in the future.

The primary motivation is to improve block placement (the cold attribute
affects the static branch prediction heuristics).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194943 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-17 02:06:35 +00:00
Andrew Trick
bb756ca244 Added a size field to the stack map record to handle subregister spills.
Implementing this on bigendian platforms could get strange. I added a
target hook, getStackSlotRange, per Jakob's recommendation to make
this as explicit as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194942 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-17 01:36:23 +00:00
Matt Arsenault
94437c9691 Use right address space pointer size
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194940 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-17 00:06:39 +00:00
Hal Finkel
bebe48dbfe Add a loop rerolling pass
This adds a loop rerolling pass: the opposite of (partial) loop unrolling. The
transformation aims to take loops like this:

for (int i = 0; i < 3200; i += 5) {
  a[i]     += alpha * b[i];
  a[i + 1] += alpha * b[i + 1];
  a[i + 2] += alpha * b[i + 2];
  a[i + 3] += alpha * b[i + 3];
  a[i + 4] += alpha * b[i + 4];
}

and turn them into this:

for (int i = 0; i < 3200; ++i) {
  a[i] += alpha * b[i];
}

and loops like this:

for (int i = 0; i < 500; ++i) {
  x[3*i] = foo(0);
  x[3*i+1] = foo(0);
  x[3*i+2] = foo(0);
}

and turn them into this:

for (int i = 0; i < 1500; ++i) {
  x[i] = foo(0);
}

There are two motivations for this transformation:

  1. Code-size reduction (especially relevant, obviously, when compiling for
code size).

  2. Providing greater choice to the loop vectorizer (and generic unroller) to
choose the unrolling factor (and a better ability to vectorize). The loop
vectorizer can take vector lengths and register pressure into account when
choosing an unrolling factor, for example, and a pre-unrolled loop limits that
choice. This is especially problematic if the manual unrolling was optimized
for a machine different from the current target.

The current implementation is limited to single basic-block loops only. The
rerolling recognition should work regardless of how the loop iterations are
intermixed within the loop body (subject to dependency and side-effect
constraints), but the significant restriction is that the order of the
instructions in each iteration must be identical. This seems sufficient to
capture all current use cases.

This pass is not currently enabled by default at any optimization level.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194939 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 23:59:05 +00:00
Hal Finkel
64fa501b10 Apply the InstCombine fptrunc sqrt optimization to llvm.sqrt
InstCombine, in visitFPTrunc, applies the following optimization to sqrt calls:

  (fptrunc (sqrt (fpext x))) -> (sqrtf x)

but does not apply the same optimization to llvm.sqrt. This is a problem
because, to enable vectorization, Clang generates llvm.sqrt instead of sqrt in
fast-math mode, and because this optimization is being applied to sqrt and not
applied to llvm.sqrt, sometimes the fast-math code is slower.

This change makes InstCombine apply this optimization to llvm.sqrt as well.

This fixes the specific problem in PR17758, although the same underlying issue
(optimizations applied to libcalls are not applied to intrinsics) exists for
other optimizations in SimplifyLibCalls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194935 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 21:29:08 +00:00
Matt Arsenault
e6e811277f Fix assert on unaligned access to global with different address space size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194934 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 20:50:54 +00:00
Matt Arsenault
4fe5b640ee Fix codegen for null different sized pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194932 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 20:24:41 +00:00
Vincent Lejeune
4110797853 R600: Make dot_4 instructions predicable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194927 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 16:24:41 +00:00
Benjamin Kramer
e9cdbf68e5 InstCombine: fold (A >> C) == (B >> C) --> (A^B) < (1 << C) for constant Cs.
This is common in bitfield code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194925 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 16:00:48 +00:00
Matt Arsenault
74c996cbd1 Use correct size for address space in BasicAA.
The tests just hit this with a different sized
address space since I haven't figured out how
to use this to break it.

I thought I committed this a long time ago,
and I'm not sure why missing this hasn't caused
any problems.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194903 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 00:36:43 +00:00
Eric Christopher
87fd14d9b5 For dwarf4 use the correct form for referencing debug_loc locations,
and update test cases accordingly.

This doesn't affect the output dumped using llvm-dwarfdump, but
readelf does now dump the debug_loc section.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194898 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-16 00:18:40 +00:00
Ana Pazos
a53bf06f7a Implemented aarch64 Neon scalar vmulx_lane intrinsics
Implemented aarch64 Neon scalar vfma_lane intrinsics
Implemented aarch64 Neon scalar vfms_lane intrinsics

Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64
intrinsics (v1f64 parameter type) using Neon scalar instructions.

Implemented legacy vfma_lane_f64, vfms_lane_f64,
vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type)
using Neon scalar instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194888 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 23:32:10 +00:00
Arnold Schwaighofer
4634338655 LoopVectorizer: Use abi alignment for accesses with no alignment
When we vectorize a scalar access with no alignment specified, we have to set
the target's abi alignment of the scalar access on the vectorized access.
Using the same alignment of zero would be wrong because most targets will have a
bigger abi alignment for vector types.

This probably fixes PR17878.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194876 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 23:09:33 +00:00
Chad Rosier
5758c3c832 [AArch64] Fix the scalar NEON ACLE functions so that they return float/double
rather than the vector equivalent.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194853 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 21:28:10 +00:00
Rui Ueyama
8a631b2cbe Path: Recognize COFF import library file magic.
Summary: Make identify_magic to recognize COFF import file.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2165

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194852 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 21:22:02 +00:00
Manman Ren
c160efc28b ArgumentPromotion: correctly transfer TBAA tags and alignments.
We used to use std::map<IndicesVector, LoadInst*> for OriginalLoads, and when we
try to promote two arguments, they will both write to OriginalLoads causing
created loads for the two arguments to have the same original load. And the same
tbaa tag and alignment will be put to the created loads for the two arguments.

The fix is to use std::map<std::pair<Argument*, IndicesVector>, LoadInst*>
for OriginalLoads, so each Argument will write to different parts of the map.

PR17906


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194846 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 20:41:15 +00:00
Bob Wilson
cc7052343e Avoid illegal integer promotion in fastisel
Stop folding constant adds into GEP when the type size doesn't match.
Otherwise, the adds' operands are effectively being promoted, changing the
conditions of an overflow.  Results are different when:

    sext(a) + sext(b) != sext(a + b)

Problem originally found on x86-64, but also fixed issues with ARM and PPC,
which used similar code.

<rdar://problem/15292280>

Patch by Duncan Exon Smith!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194840 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 19:09:27 +00:00
Tom Stellard
5cddda6d13 R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()
This fixes a crash with GNOME settings manager.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194836 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 18:26:45 +00:00
Daniel Sanders
8363c52d6d [mips][msa] Merge basic_operations_little.ll into basic_operations.ll.
Now that FileCheck supports multiple check prefixes, we don't need to keep the
little and big endian versions of this test separate anymore. Merge them back
together.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194826 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 17:24:41 +00:00
Cameron McInally
28e12e9f02 Add AVX512 unmasked FMA intrinsics and support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194824 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 17:01:14 +00:00
Daniel Sanders
ea28aafa83 Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 type
Summary:
When getConstant() is called for an expanded vector type, it is split into
multiple scalar constants which are then combined using appropriate build_vector
and bitcast operations.

In addition to the usual big/little endian differences, the case where the
element-order of the vector does not have the same endianness as the elements
themselves is also accounted for.  For example, for v4i32 on big-endian MIPS,
the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is
<0123,4567,89AB,CDEF>.
Handling this case turns out to be a nop since getConstant() returns a splatted
vector (so reversing the element order doesn't change the value)

This fixes a number of cases in MIPS MSA where calling getConstant() during
operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF
into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger
differences between illegal and legal types such as legalizing v2i64 into v8i16.

lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling
getConstant() so this function has been updated in the same patch.

For the sake of transparency, the steps I've taken since the review are:
* Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed
  that the MIPS tests were falsely passing because a polymorphic function was
  not actually polymorphic in the reviewed patch.
* Fixed the tests that were now failing. This involved deleting the code to
  handle the MIPS MSA element-order (which was previously doing an byte-order
  swap instead of an element-order swap). This left
  isVectorEltOrderLittleEndian() unused and it was deleted.
* Fixed build failures caused by rebasing beyond r194467-r194472. These build
  failures involved the bset, bneg, and bclr instructions added in these commits
  using lowerMSASplatImm() in a way that was no longer valid after this patch.
  Some of these were fixed by calling SelectionDAG::getConstant() instead,
  others were fixed by a new function getBuildVectorSplat() that provided the
  removed functionality of lowerMSASplatImm() in a more sensible way.

Reviewers: bkramer

Reviewed By: bkramer

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194811 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 12:56:49 +00:00
Justin Holewinski
4d748eb0e4 [NVPTX] Fix handling of indirect calls
Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194810 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 12:30:04 +00:00
Daniel Sanders
ca795b61be [mips][msa] Build all the tests in little and big endian modes and correct an incorrect test.
Summary:
This patch (correctly) breaks some MSA tests by exposing the cases when
SelectionDAG::getConstant() produces illegal types. These have been temporarily
marked XFAIL and the XFAIL flag will be removed when
SelectionDAG::getConstant() is fixed.

There are three categories of failure:
* Immediate instructions are not selected in one endian mode.
* Immediates used in ldi.[bhwd] must be different according to endianness.
  (this only affects cases where the 'wrong' ldi is used to load the correct
   bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...)))
* Non-immediate instructions that rely on immediates affected by the
  previous two categories as part of their match pattern.
  For example, the bset match pattern is the vector equivalent of
  'ws | (1 << wt)'.

One test needed correcting to expect different output depending on whether big
or little endian was in use. This test was
test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category
of failure shown above. The little endian version of this test is named
basic_operations_little.ll and will be merged back into basic_operations.ll in
a follow up commit now that FileCheck supports multiple check prefixes.

Reviewers: bkramer, jacksprat, dsanders

Reviewed By: dsanders

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1972

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194806 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 11:04:16 +00:00
Alexey Samsonov
ec3ce8a99d Redirect unused test case output to /dev/null
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194798 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 09:36:58 +00:00
Zoran Jovanovic
42cb3abadd Use instr mapping for microMIPS in llvm-mc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194792 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 08:07:34 +00:00
Bob Wilson
4b8991424a Reapply "[asan] Poor man's coverage that works with ASan"
I was able to successfully run a bootstrapped LTO build of clang with
r194701, so this change does not seem to be the cause of our failing
buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194789 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 07:16:09 +00:00
Andrew Trick
728eb5fbea Platform proof a test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194788 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 05:52:56 +00:00
Matt Arsenault
6dd44d3b7f Add instcombine visitor for addrspacecast
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194786 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 05:45:08 +00:00
Matt Arsenault
509a492442 Add target hook to prevent folding some bitcasted loads.
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)

On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.

Patch by Micah Villmow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 04:42:23 +00:00
Peter Zotov
a0846f4143 [OCaml] Add REQUIRES: native, object-emission to the Target test
While the test would work with any compiled in target with object
emission support, it's nontrivial to formulate this condition in
lit, so a conservative restriction is used instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194781 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 03:43:51 +00:00
Bob Wilson
2475da80ed Revert "[asan] Poor man's coverage that works with ASan"
This reverts commit 194701. Apple's bootstrapped LTO builds have been failing,
and this change (along with compiler-rt 194702-194704) is the only thing on
the blamelist.  I will either reappy these changes or help debug the problem,
depending on whether this fixes the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194780 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 03:28:22 +00:00
Peter Zotov
b53c129da1 [OCaml] Use native target in testsuite instead of hardcoding X86
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194778 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 03:19:08 +00:00
Peter Zotov
b6703ff81b [OCaml] Add Target and TargetMachine bindings to Llvm_target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194774 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:51:57 +00:00
Peter Zotov
04deb4957a [OCaml] Refactor Llvm_target interface
This commit brings the module structure, argument order and
primitive names in Llvm_target in order with the rest of the bindings,
in preparation for adding TargetMachine API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194773 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:51:44 +00:00
Reed Kotler
1703a71495 Make all the conditional Mips 16 branches get initially set for the
short form. Constant islands will expand them if they are out of range.
Since there is not direct object emitter at this time, it does not
have any material affect because the assembler sorts this out. But we
need to know for the actual constant island work. We track the difference
by putting # 16 inst in the comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 02:21:52 +00:00
Matt Arsenault
59d3ae6cdc Add addrspacecast instruction.
Patch by Michele Scandale!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194760 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 01:34:59 +00:00
Tom Stellard
19a99df130 R600: Fix scheduling of instructions that use the LDS output queue
The LDS output queue is accessed via the OQAP register.  The OQAP
register cannot be live across clauses, so if value is written to the
output queue, it must be retrieved before the end of the clause.
With the machine scheduler, we cannot statisfy this constraint, because
it lacks proper alias analysis and it will mark some LDS accesses as
having a chain dependency on vertex fetches.  Since vertex fetches
require a new clauses, the dependency may end up spiltting OQAP uses and
defs so the end up in different clauses.  See the lds-output-queue.ll
test for a more detailed explanation.

To work around this issue, we now combine the LDS read and the OQAP
copy into one instruction and expand it after register allocation.

This patch also adds some checks to the EmitClauseMarker pass, so that
it doesn't end a clause with a value still in the output queue and
removes AR.X and OQAP handling from the scheduler (AR.X uses and defs
were already being expanded post-RA, so the scheduler will never see
them).

Reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194755 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-15 00:12:45 +00:00
Eric Christopher
5a5d116d58 Simplify testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194748 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 23:43:10 +00:00
Rui Ueyama
b850a05f2c Recognize 0x0000 as a COFF file magic.
Summary:
Some machine-type-neutral object files containing only undefined symbols
actually do exist in the Windows standard library. Need to recognize them
as COFF files.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2164

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194734 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 22:09:08 +00:00
Tim Northover
bf7329d9a0 ARM: produce friendly error for invalid inline asm
We used to perform an invalid operation on an MVT and crash, which wasn't much
fun.

Patch by Oliver Stannard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194714 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 17:15:39 +00:00
Rafael Espindola
5e9f8c3948 Add a triple and switch test to FileCheck.
On windows we don't print .weak for function definitions, so count was only
finding 1 'weak'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194713 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 17:12:32 +00:00
NAKAMURA Takumi
4e7e4d8fb4 llvm-cov.test: Remove XFAIL:arm. Seems this is passing since my tweaks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194712 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 17:08:26 +00:00
Rafael Espindola
3d47402f2e Error if we see an alias to a declaration.
In ELF and COFF an alias is just another offset in a section. There is no way
to represent an alias to something in another file.

In MachO, the spec has the N_INDR type which should allow for exactly that, but
is not currently implemented. Given that it is specified but not implemented,
we error in codegen to avoid miscompiling but don't reject aliases to
declarations in the verifier to leave the option open of implementing it.

In the past we have used alias to declarations as a way of implementing
weakref, which is why it exists in some old tests which this patch updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194705 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 13:58:06 +00:00
Kostya Serebryany
8cc5f7cd59 [asan] Poor man's coverage that works with ASan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 13:27:41 +00:00
Evgeniy Stepanov
45f5110634 [msan] Use CHECK-DAG instead of CHECK where order of instructions does not matter.
This may fix hexagon-elf bots.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 12:46:12 +00:00
Evgeniy Stepanov
34432aeb6d [msan] Fast path optimization for wrap-indirect-calls feature of MemorySanitizer.
Indirect call wrapping helps MSanDR (dynamic instrumentation companion tool
for MSan) to catch all cases where execution leaves a compiler-instrumented
module by allowing the tool to rewrite targets of indirect calls.

This change is an optimization that skips wrapping for calls when target is
inside the current module. This relies on the linker providing symbols at the
begin and end of the module code (or code + data, does not really matter).
Gold linker provides such symbols by default. GNU (BFD) linker needs a link
flag: -Wl,--defsym=__executable_start=0.

More info:
https://code.google.com/p/memory-sanitizer/wiki/MSanDR#Native_exec


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 12:29:04 +00:00
NAKAMURA Takumi
d19c4ceb26 llvm-cov.test: Tweak win32 hosts not confused by \r\n in llvm-cov's stdout.
"diff -b" -- Ignore space changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194694 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 11:45:10 +00:00
Elena Demikhovsky
f58e414405 AVX-512: Handled extractelement from mask vector;
Added VMOSHDUP/VMOVSLDUP shuffle instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 11:29:27 +00:00
Matt Arsenault
e0375295c5 R600/SI: Add testcase for problem I ran into
with the older version of the moveToVALU changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194682 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 07:57:29 +00:00
Andrew Trick
72cf01cc7c Minor extension to llvm.experimental.patchpoint: don't require a call.
If a null call target is provided, don't emit a dummy call. This
allows the runtime to reserve as little nop space as it needs without
the requirement of emitting a call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194676 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 06:54:10 +00:00
Kevin Qin
27df434c5e Add test case for AArch64 NEON instruction set misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194673 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 06:45:17 +00:00
Rafael Espindola
732cf2d598 Don't mangle \n and "
There is nothing special about quotes and newlines from the object
file point of view, only the assembler has to worry about expanding
the \n and \".

This patch then removes the special handling from the Mangler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194667 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 06:05:49 +00:00
Kevin Qin
a08063a000 Implement aarch64 neon instruction class SIMD misc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 02:44:13 +00:00
NAKAMURA Takumi
3f4c031f21 Suppress llvm-cov.test on Win32, with REQUIRES: shell
"cd" is unsupported in lit internal runner.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194652 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 02:05:41 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 01:57:32 +00:00
Yunzhong Gao
2999b2f2cc Fixing a heisenbug where the memory dependence analysis behaves differently
with and without -g.

Adding a test case to make sure that the threshold used in the memory
dependence analysis is respected. The test case also checks that debug
intrinsics are not counted towards this threshold.

Differential Revision: http://llvm-reviews.chandlerc.com/D2141



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194646 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 01:10:52 +00:00
Yuchen Wu
131a764e0e llvm-cov: Removed StringMap holding GCOVLines.
According to the hazy gcov documentation, it appeared to be technically
possible for lines within a block to belong to different source files.
However, upon further investigation, gcov does not actually support
multiple source files for a single block.

This change removes a level of separation between blocks and lines by
replacing the StringMap of GCOVLines with a SmallVector of ints
representing line numbers. This also means that the GCOVLines class is
no longer needed.

This paves the way for supporting the "-a" option, which will output
block information.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194637 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 00:32:00 +00:00
Yuchen Wu
dbb51ff01f llvm-cov: Replaced asserts with proper error handling.
Unified the interface for read functions. They all return a boolean
indicating if the read from file succeeded. Functions that previously
returned the read value now store it into a variable that is passed in
by reference instead. Callers will need to check the return value to
detect if an error occurred.

Also added a new test which ensures that no assertions occur when file
contains invalid data. llvm-cov should return with error code 1 upon
failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194635 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-14 00:07:15 +00:00
Reed Kotler
5aeb5e530e Take care of long short branch immediate instructions for mips16 in
constant islands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194630 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 23:52:18 +00:00
Tom Stellard
a2b4eb6d15 R600/SI: Add support for private address space load/store
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 23:36:50 +00:00
Tom Stellard
b52bf6a3b3 R600/SI: Prefer SALU instructions for bit shift operations
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.

This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.

This patch includes some fixes from Matt Arsenault.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 23:36:37 +00:00
Yuchen Wu
eef8b8c35c llvm-cov: Changed XFAIL targets to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194622 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 23:33:17 +00:00
Yuchen Wu
86e37f567b Added basic unit test for llvm-cov.
This test compares the output of llvm-cov against a coverage file
generated by gcov. Currently, llvm-cov does not work on certain
platforms (namely big-endian architectures such as PowerPC, among
others). These platforms are marked as XFAIL for now, but will be fixed
later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194616 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 22:50:15 +00:00
Chad Rosier
11966d7c98 [AArch64] Add support for legacy AArch32 NEON scalar shift by immediate
instructions.  This patch does not include the shift right and accumulate
instructions.  A number of non-overloaded intrinsics have been remove in favor
of their overloaded counterparts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194598 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 20:05:37 +00:00
Weiming Zhao
929bdb2379 Enable generating legacy IT block for AArch32
By default, the behavior of IT block generation will be determinated
dynamically base on the arch (armv8 vs armv7). This patch adds backend
options: -arm-restrict-it and -arm-no-restrict-it.  The former one
restricts the generation of IT blocks (the same behavior as thumbv8) for
both arches. The later one allows the generation of legacy IT block (the
same behavior as ARMv7 Thumb2) for both arches.

Clang will support -mrestrict-it and -mno-restrict-it, which is
compatible with GCC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 18:29:49 +00:00
Richard Sandiford
541c5de2fb [SystemZ] Add the general form of BCR
At the moment this is just the MC support.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194585 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 16:57:53 +00:00
Alexey Samsonov
0ab53c7112 FileCheck: fix matching of one check-prefix is a prefix of another
Summary:
Fix a case when "FileCheck --check-prefix=CHECK --check-prefix=CHECKER"
would silently ignore check-lines of the form:
  CHECKER: foo

Reviewers: dsanders

Reviewed By: dsanders

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2168

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194577 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 14:12:52 +00:00
Rafael Espindola
de9a1a2055 Remove AllowQuotesInName and friends from MCAsmInfo.
Accepting quotes is a property of an assembler, not of an object file. For
example, ELF can support any names for sections and symbols, but the gnu
assembler only accepts quotes in some contexts and llvm-mc in a few more.

LLVM should not produce different symbols based on a guess about which assembler
will be reading the code it is printing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194575 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 14:01:59 +00:00
Vladimir Medic
c0fad4d9fd Fix bug in .gpword directive parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194570 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:18:04 +00:00
Zoran Jovanovic
1206f1968b Support for microMIPS trap instruction with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194569 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 13:15:03 +00:00
Diego Novillo
563b29f8db SampleProfileLoader pass. Initial setup.
This adds a new scalar pass that reads a file with samples generated
by 'perf' during runtime. The samples read from the profile are
incorporated and emmited as IR metadata reflecting that profile.

The profile file is assumed to have been generated by an external
profile source. The profile information is converted into IR metadata,
which is later used by the analysis routines to estimate block
frequencies, edge weights and other related data.

External profile information files have no fixed format, each profiler
is free to define its own. This includes both the on-disk representation
of the profile and the kind of profile information stored in the file.
A common kind of profile is based on sampling (e.g., perf), which
essentially counts how many times each line of the program has been
executed during the run.

The SampleProfileLoader pass is organized as a scalar transformation.
On startup, it reads the file given in -sample-profile-file to
determine what kind of profile it contains.  This file is assumed to
contain profile information for the whole application. The profile
data in the file is read and incorporated into the internal state of
the corresponding profiler.

To facilitate testing, I've organized the profilers to support two file
formats: text and native. The native format is whatever on-disk
representation the profiler wants to support, I think this will mostly
be bitcode files, but it could be anything the profiler wants to
support. To do this, every profiler must implement the
SampleProfile::loadNative() function.

The text format is mostly meant for debugging. Records are separated by
newlines, but each profiler is free to interpret records as it sees fit.
Profilers must implement the SampleProfile::loadText() function.

Finally, the pass will call SampleProfile::emitAnnotations() for each
function in the current translation unit. This function needs to
translate the loaded profile into IR metadata, which the analyzer will
later be able to use.

This patch implements the first steps towards the above design. I've
implemented a sample-based flat profiler. The format of the profile is
fairly simplistic. Each sampled function contains a list of relative
line locations (from the start of the function) together with a count
representing how many samples were collected at that line during
execution. I generate this profile using perf and a separate converter
tool.

Currently, I have only implemented a text format for these profiles. I
am interested in initial feedback to the whole approach before I send
the other parts of the implementation for review.

This patch implements:

- The SampleProfileLoader pass.
- The base ExternalProfile class with the core interface.
- A SampleProfile sub-class using the above interface. The profiler
  generates branch weight metadata on every branch instructions that
  matches the profiles.
- A text loader class to assist the implementation of
  SampleProfile::loadText().
- Basic unit tests for the pass.

Additionally, the patch uses profile information to compute branch
weights based on instruction samples.

This patch converts instruction samples into branch weights. It
does a fairly simplistic conversion:

Given a multi-way branch instruction, it calculates the weight of
each branch based on the maximum sample count gathered from each
target basic block.

Note that this assignment of branch weights is somewhat lossy and can be
misleading. If a basic block has more than one incoming branch, all the
incoming branches will get the same weight. In reality, it may be that
only one of them is the most heavily taken branch.

I will adjust this assignment in subsequent patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194566 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 12:22:21 +00:00
Alexey Samsonov
7df6641654 FileCheck: fix a bug with multiple --check-prefix options.
Summary:
This fixes a subtle bug in new FileCheck feature added
in r194343. When we search for the first satisfying check-prefix,
we should actually return the first encounter of some check-prefix as a
substring, even if it's not a part of valid check-line. Otherwise
"FileCheck --check-prefix=FOO --check-prefix=BAR" with check file:

  FOO not a vaild check-line
  FOO: foo
  BAR: bar

incorrectly accepted file:

  fog
  bar

as it skipped the first two encounters of FOO, matching only BAR: line.

Reviewers: arsenm, dsanders

Reviewed By: dsanders

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D2166

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194565 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 11:56:22 +00:00
Robert Lytton
8b99622b9b XCore target: implement exception handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194564 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 10:19:31 +00:00
Vladimir Medic
c7ebe50276 This patch fixes a bug in floating point operands parsing, when instruction alias uses default register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194562 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 09:48:53 +00:00
NAKAMURA Takumi
d3df4603d9 Add XFAIL:arm again on 4 MCJIT tests, since r194558. AArch64 has been left removed.
They are failing on clang-native-arm-cortex-a9.

Please tweak MCJIT/lit.local.cfg, if this didn't satisfy bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194561 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 07:43:10 +00:00
NAKAMURA Takumi
0700a80da1 Remove XFAIL:aarch64,arm from 4 tests in test/ExecutionEngine/MCJIT.
They are reported as XPASSing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194558 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 06:28:00 +00:00
Reed Kotler
4df21b1467 Allow the code which returns the length for inline assembler to know
specifically about the .space directive. This allows us to force large
blocks of code to appear in test cases for things like constant islands
without having to make giant test cases to force things like long 
branches to take effect.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194555 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 04:37:52 +00:00
Andrew Trick
bf8b04919a Add a test case to verify that misusing anyregcc crashes as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194553 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 03:46:19 +00:00
Matt Arsenault
29f1788de9 R600: Fix selection failure on EXTLOAD
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194547 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 02:39:07 +00:00
Juergen Ributzka
c7e77f91fe SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.
This patch reapplies r193676 with an additional fix for the Hexagon backend. The
SystemZ backend has already been fixed by r194148.

The Type Legalizer recognizes that VSELECT needs to be split, because the type
is to wide for the given target. The same does not always apply to SETCC,
because less space is required to encode the result of a comparison. As a result
VSELECT is split and SETCC is unrolled into scalar comparisons.

This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG
Combiner. If a matching pattern is found, then the result mask of SETCC is
promoted to the expected vector mask type for the given target. Now the type
legalizer will split both VSELECT and SETCC.

This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.

Reviewed by Nadav

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194542 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-13 01:57:54 +00:00
Andrew Trick
7107aded17 Cleanup the stackmap operand folding code and fix a corner case.
I still don't know how to refer to the fixed operands symbolically. I
plan to look into it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194529 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:58:39 +00:00
Sebastian Pop
430b6eb419 improve dependence analysis testcases
print the name of the function on which the dependence analysis is performed
such that changes to the testcase are easier to review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194528 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:47:30 +00:00
Sebastian Pop
5230ad61fd delinearization of arrays
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194527 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:47:20 +00:00
Nadav Rotem
6c84f7ad2d Fold (iszero(A&K1) | iszero(A&K2)) -> (A&(K1|K2)) != (K1|K2) if we know that K1 and K2 are 'one-hot' (only one bit is on).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194525 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:38:59 +00:00
Nadav Rotem
f3bd3ea3fe FoldBranchToCommonDest merges branches into a single branch with or/and of the condition. It has a heuristics for estimating when some of the dependencies are processed by out-of-order processors. This patch adds another rule to the heuristics that says that if the "BonusInstruction" that we speculatively execute is used by the condition of the second branch then it is okay to hoist it. This change exposes more opportunities for other passes to transform the code. It does not matter that much that we if-convert the code because the selectiondag builder splits or/and branches into multiple branches when profitable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194524 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:37:16 +00:00
Akira Hatanaka
714e04b84a [mips] Fix a bug in function CC_MipsO32_FP64. The second double precision
argument was not being passed in $f14.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:16:18 +00:00
Akira Hatanaka
fe438bba94 [mips] Run test case with command line option -mattr=+fp64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194519 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 22:06:45 +00:00
Justin Bogner
dc6b4b4fc2 Protect user-supplied runtime library functions in LTO
Add user-supplied C runtime and compiler-rt library functions to
llvm.compiler.used to protect them from premature optimization by
passes like -globalopt and -ipsccp.  Calls to (seemingly unused)
runtime library functions can be added by -instcombine and instruction
lowering.

Patch by Duncan Exon Smith, thanks!

Fixes <rdar://problem/14740087>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194514 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:44:01 +00:00
Tim Northover
59e648e3c8 ARM: diagnose invalid system LDM/STM
The system LDM and STM instructions can't usually writeback to the base
register. The one exception is when an LDM is actually an exception-return
(i.e. contains PC in the register list).

(There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there
is no positive test).

rdar://problem/15223374

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:32:41 +00:00
Akira Hatanaka
0a227ad4d5 [mips] Fix and re-enable a test case that has been disabled for a long time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 21:03:57 +00:00
Peter Zotov
1ba15ab134 [OCaml] Dynamically link LLVM on --enable-shared builds
This commit significantly speeds up both bytecode and native
builds of LLVM clients (from ~20 second to sub-second link time),
and allows to invoke LLVM functions from OCaml toplevel.

The behavior for --disable-shared builds is unchanged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 20:55:49 +00:00
Rafael Espindola
46456f6a2f Corruptly merge constants with explicit and implicit alignments.
Constant merge can merge a constant with implicit alignment with one that has
explicit alignment. Before this change it was assuming that the explicit
alignment was higher than the implicit one, causing the result to be under
aligned in some cases.

Fixes pr17815.

Patch by Chris Smowton!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194506 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 20:21:43 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 19:13:08 +00:00
Andrew Trick
0085d5e5ae Simplify operand folding when rematerializing a load.
We already know how to fold a reload from a frameindex without
analyzing the load instruction. Generalize this to handle any
frameindex load. This streamlines the logic for rematerializing loads
from stack arguments. As a side effect, it allows stackmaps to record
a stack argument location without spilling it.

Verified no effect on codegen for llvm test-suite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194497 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 18:06:12 +00:00
Daniel Sanders
9e2838e29b [mips][msa] Enable inlinse assembly for MSA.
Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier:
  asm ("ldi.w %w0, 1", "=f"(result));

Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended
output. This is a consequence of differences in the internal handling of
the registers in each compiler. To be source-compatible between the
compilers, users must use the 'w' print-modifier.

MSA registers (including control registers) are supported in clobber lists.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 12:56:01 +00:00
Benjamin Kramer
f681437cb0 SimplifyCFG: Use existing constant folding logic when forming switch tables.
Both simpler and more powerful than the hand-rolled folding logic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194475 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 12:24:36 +00:00
Daniel Sanders
bb47fd04c9 [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:45:18 +00:00
Bradley Smith
2ca352d027 [ARM] Add support for FP_HP_extension build attribute
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194470 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:38:05 +00:00
Daniel Sanders
aee7825762 [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:31:49 +00:00
Daniel Sanders
d656c91aad [mips][msa] Change constant used in ori tests to avoid conflict with bseti (also xori to avoid bnegi)
Upcoming commit(s) are going to add support for bseti and bnegi. This would
cause some existing tests to (correctly) change behaviour and emit a different
instruction. This patch prevents this by changing the constant used in ori and
xori tests so that they will not be matchable by the bseti and bnegi patterns
when these instructions are matchable from normal IR.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:14:18 +00:00
Robert Lytton
47a4349eb6 XCore target: fix bug in aligning 'byval i8*' on the stack
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194466 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:35 +00:00
Robert Lytton
092815ce4b XCore target test for hidden declaration
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194465 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:30 +00:00
Robert Lytton
32e8528c33 Add XCore support for ATOMIC_FENCE.
ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There
is no need to emit an instructions since the XCore provides sequential
consistency.

Original patch by Richard Osborne

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194464 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:26 +00:00
Robert Lytton
c17ea93ed5 XCore target: return error for unsupported alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194463 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 10:11:05 +00:00
Yuchen Wu
0cbecb56fb Revert "Added basic unit test for llvm-cov."
This reverts commit r194451.

Not sure why the tests are failing on the buildbot. They run fine on my
local machine. Could it possibly be because of the endianness of the
architectures? The GCNO and GCDA files are little-endian encoded, and
llvm-cov expects it to remain that way. Is this a safe assumption?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194454 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 05:57:06 +00:00
Yuchen Wu
f42264e7e4 llvm-cov: Added call to update run/program counts.
Also updated test files that were generated from this change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194453 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 04:59:08 +00:00
Yuchen Wu
d99e04db6a Added basic unit test for llvm-cov.
This test compares the output of llvm-cov against a coverage file
generated by gcov. Since the source file must be in the current
directory when reading GCNO files, the test will first cd into the
Inputs directory.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194451 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 04:52:53 +00:00
Matt Arsenault
86245071b5 R600/SI: Change formatting of printed registers.
Print the range of registers used with a single letter prefix.
This better matches what the shader compiler produces and
is overall less obnoxious than concatenating all of the
subregister names together.

Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1,
it will print s[0:1] and so on.

There doesn't appear to be a straightforward way
to get the actual register info in the InstPrinter,
so this parses the generated name to print with the
new syntax.

The required test changes are pretty nasty, and register
matching regexes are now worse. Since there isn't a way to
add to a variable in FileCheck, some of the tests now don't
check the exact number of registers used, but I don't think that
will be a real problem.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:35:51 +00:00
Reed Kotler
c6d4d667a8 Change the default branch instruction to be the 16 bit variety for mips16.
This has no material effect at this time since we don't have a direct
object emitter for mips16 and the assembler can't tell them apart. I
place a comment "16 bit inst" for those so that I can tell them apart in the
output. The constant island pass has only been minimally changed to allow
this. More complete branch work is forthcoming but this is the first
step.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-12 02:27:12 +00:00
Matt Arsenault
e57a8a3d10 R600/SI: Add test that fails due to requiring i64 mul for pointers
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194433 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 23:31:02 +00:00
Andrew Trick
01846af6ed Fix the recently added anyregcc convention to handle spilled operands.
Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!"

The primary purpose of anyregcc is to prevent a patchpoint's call
arguments and return value from being spilled. They must be available
in a register, although the calling convention does not pin the
register. It's up to the front end to avoid using this convention for
calls with more arguments than allocatable registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194428 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 22:40:25 +00:00
Vincent Lejeune
70a7d5ddb4 R600: Use function inputs to represent data stored in gpr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 22:10:24 +00:00
Shuxin Yang
6c7a7c6474 Fix PR17952.
The symptom is that an assertion is triggered. The assertion was added by
me to detect the situation when value is propagated from dead blocks.
(We can certainly get rid of assertion; it is safe to do so, because propagating
 value from dead block to alive join node is certainly ok.)

  The root cause of this bug is : edge-splitting is conducted on the fly,
the edge being split could be a dead edge, therefore the block that 
split the critial edge needs to be flagged "dead" as well.

  There are 3 ways to fix this bug:
  1) Get rid of the assertion as I mentioned eariler 
  2) When an dead edge is split, flag the inserted block "dead".
  3) proactively split the critical edges connecting dead and live blocks when
     new dead blocks are revealed.

  This fix go for 3) with additional 2 LOC.

  Testing case was added by Rafael the other day.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194424 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 22:00:23 +00:00
Akira Hatanaka
5635de519a [mips] Partially revert r193641. Stack alignment should not be determined by
the floating point register mode.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 21:49:03 +00:00
Simon Atanasyan
fe9ce427d0 Add support for DT_VERxxx and DT_MIPS_xxx .dynamic section entries to the
llvm-readobj.

The patch reviewed by Michael Spencer.
http://llvm-reviews.chandlerc.com/D2113

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194421 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 20:51:48 +00:00
Artyom Skrobov
ef572e31e2 [ARM] Add support for MVFR2 which is new in ARMv8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:56:13 +00:00
Justin Holewinski
07a5d3dc3d [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment of function parameters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194410 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:28:19 +00:00
Justin Holewinski
0df3ce333b [NVPTX] Fix logic error in loading vector parameters of more than 4 components
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194409 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:28:16 +00:00
Chad Rosier
4c433cf673 [AArch64] The shift right/left and insert immediate builtins expect 3
source operands, a vector, an element to insert, and a shift amount.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194406 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 19:11:11 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 18:04:07 +00:00
Daniel Sanders
028e4d27b1 Vector forms of SHL, SRA, and SRL can be constant folded using SimplifyVBinOp too
Reviewers: dsanders

Reviewed By: dsanders

CC: llvm-commits, nadav

Differential Revision: http://llvm-reviews.chandlerc.com/D1958

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 17:23:41 +00:00
Matheus Almeida
12f06e1e09 [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194391 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:46:20 +00:00
Matheus Almeida
e7a21331b5 [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194390 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:38:55 +00:00
Matheus Almeida
9d48b69e37 [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194389 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:31:46 +00:00
Matheus Almeida
1b2034d969 [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194387 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:24:53 +00:00
Matheus Almeida
416a158893 [mips][msa] CHECK-DAG-ize MSA 2r.ll test.
No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 16:16:53 +00:00
Rafael Espindola
a2b3882c10 Add a testcase for pr17852.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194385 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 15:37:52 +00:00
Hal Finkel
f14beced2b Add PPC option for full register names in asm
On non-Darwin PPC systems, we currently strip off the register name prefix
prior to instruction printing. So instead of something like this:

  mr r3, r4

we print this:

  mr 3, 4

The first form is the default on Darwin, and is understood by binutils, but not
yet understood by our integrated assembler. Once our integrated-as understands
full register names as well, this temporary option will be replaced by tying
this functionality to the verbose-asm option. The numeric-only form is
compatible with legacy assemblers and tools, and is also gcc's default on most
PPC systems. On the other hand, it is harder to read, and there are some
analysis tools that expect full register names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194384 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:58:40 +00:00
Peter Zotov
fa6ab4393e [OCaml] Add missing Llvm_target functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194382 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:47:28 +00:00
Peter Zotov
786a43e2d8 [OCaml] Accept context explicitly in Llvm_target functions
Llvm_target.intptr_type used to implicitly use global context. As
none of other functions in OCaml bindings do, it is changed to
accept context explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194381 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:47:20 +00:00
Peter Zotov
26f3bd8966 [OCaml] Make Llvm_target.DataLayout.t automatically managed
This breaks the API by removing Llvm_target.DataLayout.dispose.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194380 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 14:47:11 +00:00
Evgeniy Stepanov
4590b8c090 [msan] Propagate origin for insertvalue, extractvalue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-11 13:37:10 +00:00
NAKAMURA Takumi
a22657f457 Mark 36 tests as XFAIL:vg_leak in llvm/test/TableGen.
In historical reason, tblgen is not strictly required to be free from memory leaks.
For now, I mark them as XFAIL, they could be fixed, though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194353 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 14:26:08 +00:00
NAKAMURA Takumi
c48f086d7c Remove 6 of XFAIL(s) in llvm/test/TableGen, since r193736. They have been XPASSing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 14:25:44 +00:00
Bill Wendling
855c29d82c Revert "Resurrect r191017 " GVN proceeds in the presence of dead code" plus a fix to PR17307 & 17308."
This causes PR17852.

This reverts commit d93e8a06b2.

Conflicts:
	test/Transforms/GVN/cond_br2.ll

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 07:34:34 +00:00
Nadav Rotem
30150a128c SimplifyCFG has a heuristics for out-of-order processors that decides when it is worthwhile to merge branches. It tries to estimate if the operands of the instruction that we want to hoist are ready. This commit marks function arguments as 'ready' because they require no calculation. This boosts libquantum and a few other workloads from the testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194346 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 04:13:31 +00:00
Matt Arsenault
9c410777d1 Resolve TODO in test now that filecheck has multiple check prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194344 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 02:16:47 +00:00
Matt Arsenault
ee4f5eae1c Allow multiple check prefixes in FileCheck.
This is useful if you want to run multiple variations
of a single test, and the majority of check lines
should be the same.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194343 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 02:04:09 +00:00
Matt Arsenault
432bdf6571 Teach MergeFunctions about address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194342 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 01:44:37 +00:00
Matt Arsenault
328c61d60c Use variable for register name in test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194338 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 00:57:17 +00:00
Reed Kotler
50d3b27f43 Mostly finish up constant islands port for Mips for load constants.
Still need to finish the branch part. Still lots more review of the code,
clean up and testing. 



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194337 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-10 00:09:26 +00:00
Akira Hatanaka
95830221bd [mips] Make sure there is a chain edge dependency between loads that read
formal arguments on the stack and stores created afterwards. We need this to
ensure tail call optimized function calls do not write over the argument area
of the stack before it is read out.
 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194309 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-09 02:38:51 +00:00
Juergen Ributzka
d4f5a61567 [Stackmap] Materialize the jump address within the patchpoint noop slide.
This patch moves the jump address materialization inside the noop slide. This
enables patching of the materialization itself or its complete removal. This
patch also adds the ability to define scratch registers that can be used safely
by the code called from the patchpoint intrinsic. At least one scratch register
is required, because that one is used for the materialization of the jump
address. This patch depends on D2009.

Differential Revision: http://llvm-reviews.chandlerc.com/D2074

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194306 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-09 01:51:33 +00:00
Juergen Ributzka
623d2e618f [Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.
The idea of the AnyReg Calling Convention is to provide the call arguments in
registers, but not to force them to be placed in a paticular order into a
specified set of registers. Instead it is up tp the register allocator to assign
any register as it sees fit. The same applies to the return value (if
applicable).

Differential Revision: http://llvm-reviews.chandlerc.com/D2009

Reviewed by Andy

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194293 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 23:28:16 +00:00
Jim Grosbach
dc7eb3e023 X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable()
On darwin, when trying to create compact unwind info, a .cfi_cfa_def
directive would case an llvm_unreachable() to be hit. Back off when we
see this directive and generate the regular DWARF style eh_frame.

rdar://15406518

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194285 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 22:33:06 +00:00
Quentin Colombet
f0c6ab6f00 [VirtRegMap] Fix for PR17825. Do not ignore noreturn definitions when setting
isPhysRegUsed if the unwind information is required.
Indeed, the runtime may need a correct stack to be able to unwind the call.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194271 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 18:14:17 +00:00
Tim Northover
323ac85d6a ARM: fold prologue/epilogue sp updates into push/pop for code size
ARM prologues usually look like:
    push {r7, lr}
    sub sp, sp, #4

If code size is extremely important, this can be optimised to the single
instruction:
    push {r6, r7, lr}

where we don't actually care about the contents of r6, but pushing it subtracts
4 from sp as a side effect.

This should implement such a conversion, predicated on the "minsize" function
attribute (-Oz) since I've yet to find any code it actually makes faster.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194264 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 17:18:07 +00:00
Artyom Skrobov
2b01682aa7 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194263 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:25:50 +00:00
Artyom Skrobov
c5c991bf31 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194262 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:17:14 +00:00
Artyom Skrobov
fa840ba402 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 16:16:30 +00:00
Zoran Jovanovic
c9af1add85 Test for microMIPS trap instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194258 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 14:55:31 +00:00
NAKAMURA Takumi
6af8781854 llvm-ar: Let opening a directory failed in llvm-ar.
Linux cannot open directories with open(2), although cygwin and *bsd can.

Motivation: The test, Object/directory.ll, had been failing with --target=cygwin on Linux. XFAIL was improper for host issues.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194257 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 12:35:56 +00:00
Matheus Almeida
de712386cd [mips][msa] Update encoding of LDI instruction.
The encoding was updated in MSA r1.07.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194255 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 10:43:11 +00:00
Artyom Skrobov
1b91231347 [ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-08 09:16:31 +00:00
David Majnemer
0ab2058852 IR: Do not canonicalize constant GEPs into an out-of-bounds array access
Summary:
Consider a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 0)

If we proceeded to GEP the aforementioned object by 8, would form a GEP of:
i8* getelementptr ({ [2 x i8], i32, i8, [3 x i8] }* @main.c, i32 0, i32 0, i64 8)

Note that we would go through the first array member, causing an
out-of-bounds accesses.  This is problematic because we might get fooled
if we are trying to evaluate loads using this GEP, for example, based
off of an object with a constant initializer where the array is zero.

This fixes PR17732.

Reviewers: nicholas, chandlerc, void

Reviewed By: void

CC: llvm-commits, echristo, void, aemerson

Differential Revision: http://llvm-reviews.chandlerc.com/D2093

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 22:15:53 +00:00
Zoran Jovanovic
9f471750fa Support for microMIPS trap instructions 1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-07 14:35:24 +00:00
Vincent Lejeune
69239a98b6 R600: Fix LowerUDIVREM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 17:36:04 +00:00
Benjamin Kramer
02707cb98e Add test case for PR12377, it was fixed by r194116.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:55:41 +00:00
Vladimir Medic
2263a2ca72 Implement gpword directive for mips, test case added. Stype changes using clang-format are also included.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194145 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 11:27:05 +00:00
Peter Zotov
ec7270c966 [OCaml] Impement Llvm_irreader, bindings to LLVM assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:25 +00:00
Peter Zotov
ba0c7cd012 [OCaml] Implement Llvm.string_of_llvalue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194136 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 09:21:08 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:25:49 +00:00
Andrew Trick
10bb82e54f Rewrite SCEV's backedge taken count computation.
Patch by Michele Scandale!

Rewrite of the functions used to compute the backedge taken count of a
loop on LT and GT comparisons.

I decided to split the handling of LT and GT cases becasue the trick
"a > b == -a < -b" in some cases prevents the trip count computation
due to the multiplication by -1 on the two operands of the
comparison. This issue comes from the conservative computation of
value range of SCEVs: taking the negative SCEV of an expression that
have a small positive range (e.g. [0,31]), we would have a SCEV with a
fullset as value range.

Indeed, in the new rewritten function I tried to better handle the
maximum backedge taken count computation when MAX/MIN expression are
used to handle the cases where no entry guard is found.

Some test have been modified in order to check the new value correctly
(I manually check them and reasoning on possible overflow the new
values seem correct).

I finally added a new test case related to the multiplication by -1
issue on GT comparisons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194116 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-06 02:08:26 +00:00
Andrew Trick
dc8224def3 Slightly change the way stackmap and patchpoint intrinsics are lowered.
MorphNodeTo is not safe to call during DAG building. It eagerly
deletes dependent DAG nodes which invalidates the NodeMap. We could
expose a safe interface for morphing nodes, but I don't think it's
worth it. Just create a new MachineNode and replaceAllUsesWith.

My understaning of the SD design has been that we want to support
early target opcode selection. That isn't very well supported, but
generally works. It seems reasonable to rely on this feature even if
it isn't widely used.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194102 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 22:44:04 +00:00
Tim Northover
f635ab8eab ARM: permit bare dmb/dsb/isb aliases on Cortex-M0
Cortex-M0 supports these 32-bit instructions despite being Thumb1 only
(mostly). We knew about that but not that the aliases without the default "sy"
operand were also permitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194094 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 21:36:02 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 17:42:05 +00:00
Michael Gottesman
f23af8bfd8 [objc-arc] Convert the one directional retain/release relation assert to a conditional check + fail.
Due to the previously added overflow checks, we can have a retain/release
relation that is one directional. This occurs specifically when we run into an
additive overflow causing us to drop state in only one direction. If that
occurs, we should bail and not optimize that retain/release instead of
asserting.

Apologies for the size of the testcase. It is necessary to cause the additive
cfg overflow to trigger.

rdar://15377890

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194083 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 16:02:40 +00:00
Alp Toker
04ae34b0aa Provide a test input for opt
This was only working previously due to a quirk in the way lit
concatenates script commands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194078 91177308-0d34-0410-b5e6-96231b3b80d8
2013-11-05 13:57:34 +00:00