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102 Commits

Author SHA1 Message Date
Owen Anderson
90c579de5a Reapply r110396, with fixes to appease the Linux buildbot gods. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 18:33:48 +00:00
Owen Anderson
1f74590e9d Revert r110396 to fix buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-06 00:23:35 +00:00
Owen Anderson
9ccaf53ada Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static 
ID member as the sole unique type identifier.  Clean up APIs related to this change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-05 23:42:04 +00:00
Jakob Stoklund Olesen
628a79771b When no memoperands are present, assume unaligned, volatile. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107114 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-29 01:13:07 +00:00
Dan Gohman
fe60104ac9 Use pre-increment instead of post-increment when the result is not used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106542 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-22 15:08:57 +00:00
Evan Cheng
d95ea2da28 Fix PR7421: bug in kill transferring logic. It was ignoring loads / stores which have already been processed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106481 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:21:14 +00:00
Jim Grosbach
400c95fe38 Make sure to skip dbg_value instructions when finding an insertion point for 
the combined load/store instruction. rdar://7797940

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105982 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-15 00:41:09 +00:00
Jim Grosbach
db03adb346 be slightly more subtle about skipping dbg_value instructions; otherwise, if a 
dbg_value immediately follows a sequence of ldr/str instructions that should
be combined into an ldm/stm and is the last instruction in the block, then
combine may end up being skipped.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105758 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-09 22:21:24 +00:00
Jim Grosbach
6335ac67b6 fix copy/paste/modify think-o 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105653 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-08 22:53:32 +00:00
Jim Grosbach
8af44b687b Another fix to prevent debug info from affecting codegen. rdar://7797940 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 17:57:34 +00:00
Jim Grosbach
958e4e1967 more dbg_value adjustments so debug info doesn't affect codegen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 01:23:30 +00:00
Jim Grosbach
d089a7ac70 fix typo 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-04 00:15:00 +00:00
Jim Grosbach
3de755bb40 Teach the ARM load-store optimizer to deal with dbg_value instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-03 22:41:15 +00:00
Jim Grosbach
18f30e6f5e Clean up 80 column violations. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 21:53:11 +00:00
Dan Gohman
ae541aad5c Add more const qualifiers for LLVM IR pointers in CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101342 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-04-15 04:33:49 +00:00
Jim Grosbach
9a52d0c352 vldm/vstm can only do up to 16 double-word registers at a time. 
Radar 7797856

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-26 18:41:09 +00:00
Bob Wilson
c88d072293 pr6652: Use LDM to restore PC to the return address on ARMv4. 
Patch by John Tytgat!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99096 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-20 22:20:40 +00:00
Bob Wilson
2d357f6b44 Remove redundant writeback flag in ARM addressing mode 5. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98648 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 18:38:09 +00:00
Bob Wilson
ab3460519e Remove the writeback flag from ARM's address mode 4. Now that we have separate 
instructions for ld/st with writeback, the flag is completely redundant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 17:46:45 +00:00
Bob Wilson
8d95e0be13 Wrap a long line and add some parens to be consistent. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98596 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 00:31:15 +00:00
Bob Wilson
815baebe1c Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 01:08:20 +00:00
Bob Wilson
3943ac38c9 Combine the code to build VLDM and VSTM instructions, since they are 
mostly the same.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 00:43:32 +00:00
Bob Wilson
e4193b20fd Tidy up. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98398 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-12 22:50:09 +00:00
Bob Wilson
bbf39b0fd9 pr6480: Don't try producing ld/st-multiple instructions when the address is 
an undef value.  This is only going to come up for bugpoint-reduced tests --
correct programs will not access memory at undefined addresses -- so it's not
worth the effort of doing anything more aggressive.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97745 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-04 21:04:38 +00:00
Jakob Stoklund Olesen
9e6396d05e Stay away from str <undef> in ARMLoadStoreOpt. This pass does not understand 
<undef> operands, and can cause scavenger failures when it translates
<kill,undef> to <kill>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97046 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-24 18:57:08 +00:00
Evan Cheng
3f7aa79c2a Load / store multiple instructions cannot load / store sp. Sorry, can't come up with a reasonable test case. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96023 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:17:21 +00:00
Jakob Stoklund Olesen
069e100f9a Don't fold insufficiently aligned ldr/str into ldm/stm instructions. 
An unaligned ldr causes a trap, and is then emulated by the kernel with
awesome performance. The darwin kernel does not emulate unaligned ldm/stm
Thumb2 instructions, so don't generate them.

This fixes the miscompilation of Multisource/Applications/JM/lencod for Thumb2.

Generating unaligned ldr/str pairs from a 16-bit aligned memcpy is probably
also a bad idea, but that is beyond the scope of this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93393 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-14 00:54:10 +00:00
Jakob Stoklund Olesen
1dbc38f52e Move kill flags when the same register occurs more than once in a sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92058 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 21:34:03 +00:00
Jakob Stoklund Olesen
158a2263bd Handle undef operands properly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92054 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 21:28:42 +00:00
Jakob Stoklund Olesen
6528966eae Make insert position available to MergeOpsUpdate. 
Rearrange arguments.
No functional changes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92053 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 21:28:37 +00:00
Jakob Stoklund Olesen
3063aed8d2 Perform kill flag calculations in new method. No functional changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92052 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 21:28:31 +00:00
Jakob Stoklund Olesen
f8e33e513f Move repeated code to a new method. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92051 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 21:28:23 +00:00
Douglas Gregor
cabdd7425d Fix a bunch of little errors that Clang complains about when its being pedantic 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91764 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-19 07:05:23 +00:00
Chris Lattner
7896c9f436 improve portability to avoid conflicting with std::next in c++'0x. 
Patch by Howard Hinnant!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90365 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-03 00:50:42 +00:00
Evan Cheng
0cd22dd738 When expanding t2STRDi8 r, r to two stores, add kill markers correctly. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88734 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-14 01:50:00 +00:00
Jim Grosbach
e5165490b7 Use Unified Assembly Syntax for the ARM backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86494 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-09 00:11:35 +00:00
Nick Lewycky
f5a86f45e7 Remove includes of Support/Compiler.h that are no longer needed after the 
VISIBILITY_HIDDEN removal.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:57:41 +00:00
Nick Lewycky
6726b6d75a Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces. 
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-25 06:33:48 +00:00
Evan Cheng
faf93aa233 Load / store multiple was missing opportunites when the load / store bundles are at the end of the bb. Test case is already in, the bug is exposed by subsequent commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84842 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-22 06:47:35 +00:00
Evan Cheng
d20d658675 Change ld/st multiples to explicitly model the writeback to base register. This fixes most of the -ldstopti-before-sched2 regressions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83191 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-10-01 01:33:39 +00:00
Evan Cheng
fa1be5d991 Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83058 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-29 07:07:30 +00:00
Evan Cheng
e298ab26b1 Enable pre-regalloc load / store multiple pass for Thumb2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82893 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-27 09:46:04 +00:00
Evan Cheng
8f05c1004a Add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82836 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-26 02:43:36 +00:00
Evan Cheng
eef490f459 Code clean up and prepare for Thumb2 support. No functionality changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82805 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-25 21:44:53 +00:00
Dan Gohman
c76909abfe Improve MachineMemOperand handling. 
- Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions.
   This eliminates MachineInstr's std::list member and allows the data to be
   created by isel and live for the remainder of codegen, avoiding a lot of
   copying and unnecessary translation. This also shrinks MemSDNode.
 - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated
   fields for MachineMemOperands.
 - Change MemSDNode to have a MachineMemOperand member instead of its own
   fields with the same information. This introduces some redundancy, but
   it's more consistent with what MachineInstr will eventually want.
 - Ignore alignment when searching for redundant loads for CSE, but remember
   the greatest alignment.

Target-specific code which previously used MemOperandSDNodes with generic
SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range
so that the SelectionDAG framework knows that MachineMemOperand information
is available.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-25 20:36:54 +00:00
Jim Grosbach
e11a8f565c Update register class references to use the global constant ARM::*RegisterClass names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-09-11 19:49:06 +00:00
Jakob Stoklund Olesen
c0823fe7c6 Simplify RegScavenger::FindUnusedReg. 
- Drop the Candidates argument and fix all callers. Now that RegScavenger
  tracks available registers accurately, there is no need to restict the
  search.
- Make sure that no aliases of the found register are in use. This was a potential bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79369 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-18 21:14:54 +00:00
Owen Anderson
1d0be15f89 Push LLVMContexts through the IntegerType APIs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78948 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-13 21:58:54 +00:00
Jim Grosbach
764ab52dd8 Whitespace cleanup. Remove trailing whitespace. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-11 15:33:49 +00:00
Evan Cheng
8fb903604e Code refactoring. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78455 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-08-08 03:20:32 +00:00