Jim Grosbach
08bd54987f
Add custom encoder for the 's' bit denoting whether an ARM arithmetic
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instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116360 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 23:00:24 +00:00
Jim Grosbach
f59818b81a
Add MOVi ARM encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116321 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 18:09:12 +00:00
Jim Grosbach
8e157302f4
Nuke unused wrapper function.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116318 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:53:25 +00:00
Jim Grosbach
0de6ab3c43
Add encoding information for the remainder of the generic arithmetic
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ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-12 17:11:26 +00:00
Jim Grosbach
42fac8ee3b
MC machine encoding for simple aritmetic instructions that use a shifted
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register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-11 23:16:21 +00:00
Jim Grosbach
56ac907c57
Implement a few more binary encoding bits. Still very early stage proof-of-
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concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 21:45:55 +00:00
Jim Grosbach
3e09413c2c
Reapply 116059, this time without the fatfingered pasto at the top.
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''const'ify getMachineOpValue() and associated helpers.'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:45:54 +00:00
Jim Grosbach
2cee75a254
Reverting 116059. Bots are unhappy with it.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 17:28:40 +00:00
Jim Grosbach
461caba214
'const'ify getMachineOpValue() and associated helpers.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 16:52:44 +00:00
Jim Grosbach
58f38bfa24
Enable binary encoding of some simple instructions.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116022 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:39:21 +00:00
Jim Grosbach
bade37bb8b
Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116018 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-08 00:21:28 +00:00
Jim Grosbach
d6d4b42ba4
Trivial MC code emitter shell. No instruction forms actually handled yet.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115993 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 22:12:50 +00:00
Jim Grosbach
9af82ba42b
Include the auto-generated bits for machine encoding.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115987 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 21:57:55 +00:00
Jim Grosbach
ae93ed1dd7
ARM instruction don't have instruction prefixes, so remove the helper functions
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for them from the MCCodeEmitter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115975 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-07 20:41:30 +00:00
Michael J. Spencer
895dda6fb5
Fix build.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-18 17:54:37 +00:00
Jim Grosbach
568eeedea7
Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-17 18:46:17 +00:00
