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8885 Commits

Author SHA1 Message Date
Craig Topper
0b9c5e268f Add hasSideEffects=0 to CMP*rr_REV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171130 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:08:46 +00:00
Craig Topper
5e6a86c7f0 Add mayLoad, mayStore, and hasSideEffects tags to BT/BTS/BTR/BTC instructions. Shouldn't change any functionality since they don't have patterns to select them. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171128 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-27 02:01:33 +00:00
Craig Topper
e9fd6ad567 Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171123 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:27:57 +00:00
Craig Topper
ee5b63cb52 Add hasSideEffects=0 to some atomic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171122 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 23:08:12 +00:00
Craig Topper
b87a5b3a1f Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171121 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 22:19:23 +00:00
Craig Topper
37cb8398c8 Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:30:22 +00:00
Craig Topper
a85cbfeba7 Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 21:04:30 +00:00
Craig Topper
0a5ead92ff Merge still more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:54:43 +00:00
Craig Topper
07555fc640 Merge more SSE/AVX instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 07:20:35 +00:00
Craig Topper
755841d9d7 Fix 80 column violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171097 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:53 +00:00
Craig Topper
6f9d44e072 Fix class name in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171096 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:15:09 +00:00
Craig Topper
219bc2db1f Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171095 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:14:15 +00:00
Craig Topper
02082efaab Remove 'v' from mnemonic to fix asm matching failures. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171093 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 06:02:15 +00:00
Craig Topper
3cdc3827ce Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171092 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 05:49:15 +00:00
Nadav Rotem
a05f7cbbde Reformat the docs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171091 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:59:20 +00:00
Craig Topper
09a326d3f0 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171087 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 04:36:03 +00:00
Craig Topper
1fe132ae7d Merge an AVX/SSE 256-bit and 128-bit multiclass. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171086 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:56:47 +00:00
Craig Topper
b5c590a586 Mark VANDNPD/VANDNPDS as not commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171085 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 03:48:10 +00:00
Craig Topper
174a3d3e63 Remove alignment from a bunch more VEX encoded operations in the folding tables. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171082 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:44:47 +00:00
Craig Topper
d83a73adf0 Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171081 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 02:14:19 +00:00
Craig Topper
1ac0046fa8 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171080 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 01:47:12 +00:00
Craig Topper
0f77910e6f Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171078 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-26 00:35:47 +00:00
Benjamin Kramer
99f78061e0 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171064 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 13:09:08 +00:00
Benjamin Kramer
382ed78d3f X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. 
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171063 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 12:54:19 +00:00
Nadav Rotem
a4c8a32a9f VCVTSS2SD requires a strict alignment. Thanks Elena. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171049 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-25 03:29:18 +00:00
Nick Lewycky
71f30bffcf Quiet gcc's -Wparenthesis warning. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171044 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 19:58:45 +00:00
Nadav Rotem
ace0c2fad7 Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. 
When these instructions are encoded in VEX (on AVX) there is no such requirement. This changes the folding
tables and removes the alignment restrictions from VEX-encoded instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171024 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-24 09:40:33 +00:00
Nadav Rotem
40b04a481d whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170997 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 07:33:44 +00:00
Nadav Rotem
677689cf5d Rename a function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170996 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 07:30:09 +00:00
Nadav Rotem
d54fed2786 Loop Vectorizer: Update the cost model of scatter/gather operations and make 
them more expensive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170995 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-23 07:23:55 +00:00
Benjamin Kramer
2f8a6cdfa3 X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. 
pmuludq is slow, but it turns out that all the unpacking and packing of the
scalarized mul is even slower. 10% speedup on loop-vectorized paq8p.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170985 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-22 16:07:56 +00:00
Benjamin Kramer
17347912b4 X86: Emit vector sext as shuffle + sra if vpmovsx is not available. 
Also loosen the SSSE3 dependency a bit, expanded pshufb + psra is still better
than scalarized loads. Fixes PR14590.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170984 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-22 11:34:28 +00:00
Nadav Rotem
d0696ef8c3 In some cases, due to scheduling constraints we copy the EFLAGS. 
The only way to read the eflags is using push and pop. If we don't
adjust the stack then we run over the first frame index. This is
not something that we want to do, so we have to make sure that
our machine function does not copy the flags. If it does then
we have to emit the prolog that adjusts the stack.

rdar://12896831



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170961 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 23:48:49 +00:00
Benjamin Kramer
2556c6b4b6 X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization. 
Part of PR14667.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170908 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 17:46:58 +00:00
Benjamin Kramer
739c7a83e1 X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics 
This is very mechanical, no functionality change. Preparation for PR14667.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170898 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 14:04:55 +00:00
Nadav Rotem
042a9a2666 Add a missing "virtual" keyword. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170842 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 05:02:12 +00:00
Nadav Rotem
f5637c3997 Improve the X86 cost model for loads and stores. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-21 01:33:59 +00:00
Jakob Stoklund Olesen
be06aacaa9 Add an MF argument to MI::copyImplicitOps(). 
This function is often used to decorate dangling instructions, so a
context reference is required to allocate memory for the operands.

Also add a corresponding MachineInstrBuilder method.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 22:54:02 +00:00
Roman Divacky
6af228a92a Remove MCTargetAsmLexer and its derived classes now that edis, 
its only user, is gone.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170699 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 14:43:30 +00:00
Richard Smith
ba836a2e80 Fix use-before-construction of X86TargetLowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170654 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-20 04:04:17 +00:00
Jim Grosbach
fbf3b4a076 MC: Add MCInstrDesc::mayAffectControlFlow() method. 
MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 23:38:53 +00:00
Jakob Stoklund Olesen
37a942cd52 Remove the explicit MachineInstrBuilder(MI) constructor. 
Use the version that also takes an MF reference instead.

It would technically be possible to extract an MF reference from the MI
as MI->getParent()->getParent(), but that would not work for MIs that
are not inserted into any basic block.

Given the reasonably small number of places this constructor was used at
all, I preferred the compile time check to a run time assertion.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 21:31:56 +00:00
Roman Divacky
759e3fa641 Remove edis - the enhanced disassembler. Fixes PR14654. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 19:55:47 +00:00
Paul Redmond
6da2e22dff Transform (x&C)>V into (x&C)!=0 where possible 
When the least bit of C is greater than V, (x&C) must be greater than V
if it is not zero, so the comparison can be simplified.

Although this was suggested in Target/X86/README.txt, it benefits any
architecture with a directly testable form of AND.

Patch by Kevin Schoedel


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170576 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 19:47:13 +00:00
Patrik Hagglund
e5c65911a6 Change TargetLowering::getTypeForExtArgOrReturn to take and return 
MVTs, instead of EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170537 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 12:02:25 +00:00
Patrik Hagglund
dfcf33a287 Change TargetLowering::RegisterTypeForVT to contain MVTs, instead of 
EVTs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170535 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 11:48:16 +00:00
Patrik Hagglund
0340557fb8 Change TargetLowering::findRepresentativeClass to take an MVT, instead 
of EVT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 11:30:36 +00:00
NAKAMURA Takumi
16537418f4 X86ISelLowering.cpp: Fix warnings. [-Wlogical-op-parentheses] 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170523 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 10:12:48 +00:00
Elena Demikhovsky
4b977312c7 Optimized load + SIGN_EXTEND patterns in the X86 backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170506 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 07:50:20 +00:00
Bill Wendling
034b94b170 Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-12-19 07:18:57 +00:00