6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity
76,502 Commits 39 Branches 0 Tags 277 MiB
1045a594e6
Commit Graph

3697 Commits

Author SHA1 Message Date
David Greene
1045a594e6 Implement VarListElementInit:: resolveListElementReference 
Implement VarListElementInit:: resolveListElementReference so that
lists of lists can be indexed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140882 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 20:59:49 +00:00
Jakob Stoklund Olesen
203e0b17dd Precompute a bit vector of register sub-classes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140827 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
7dcaa5b0fb Order register classes topologically. 
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140826 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen
29f018cee6 Switch to ArrayRef<CodeGenRegisterClass*>. 
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140816 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 22:28:37 +00:00
Daniel Dunbar
caf1912893 tblgen/ClangDiagnostics: Add support for split default warning "no-werror" and 
"show-in-system-header" bits, which I will be adding in Clang shortly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140741 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-29 00:29:04 +00:00
Bob Wilson
05a5c109e0 Remove old hack for compiling with gcc-4.0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140573 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 22:30:57 +00:00
Owen Anderson
0afa0094af ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-26 21:06:22 +00:00
Jakob Stoklund Olesen
c291e2f578 Add target hook for pseudo instruction expansion. 
Many targets use pseudo instructions to help register allocation.  Like
the COPY instruction, these pseudos can be expanded after register
allocation.  The early expansion can make life easier for PEI and the
post-ra scheduler.

This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140472 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-25 19:21:35 +00:00
Craig Topper
4da632e6e0 Don't allow 32-bit only instructions to be disassembled in 64-bit mode. Fixes part of PR10700. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-23 06:57:25 +00:00
Andrew Trick
83a8031336 Restore hasPostISelHook tblgen flag. 
No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140160 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 18:22:31 +00:00
Andrew Trick
4815d56bb2 ARM isel bug fix for adds/subs operands. 
Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140134 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 03:17:40 +00:00
Eric Christopher
eae5a13078 Remove more of llvmc and dependencies. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140121 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-20 00:34:27 +00:00
Jim Grosbach
7f739bee26 Thumb2 assembly parsing and encoding for TBB/TBH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 22:21:13 +00:00
David Greene
d9746fe58a Better Error Reporting 
Report missing template arguments more helpfully by supplying the name
of the missing argument in the error message.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-19 18:26:07 +00:00
Eric Christopher
04f138e225 Migrate this to use clang by default as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139936 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:36:22 +00:00
Eric Christopher
48dbeecd7e We now look for clang, then llvm-gcc, then gcc as our compiler. We don't need 
this anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139935 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-16 20:36:20 +00:00
Craig Topper
a08e255e1e Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-14 06:41:26 +00:00
Argyrios Kyrtzidis
516f52e24f [tablegen] In ClangAttrEmitter.cpp handle SourceLocation arguments to attributes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139617 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 18:41:43 +00:00
Argyrios Kyrtzidis
c9dccb8865 In ClangAttrEmitter.cpp emit code that allows attributes to keep their source range. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139598 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 16:05:43 +00:00
Craig Topper
58bbb81764 Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-13 06:54:58 +00:00
Craig Topper
038197988b Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-11 21:41:45 +00:00
Craig Topper
842f58f9be Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-11 20:23:20 +00:00
Douglas Gregor
13d8baa3fc Update Clang AST attribute reader tblgen generation to match with ASTReader change 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139414 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 21:37:29 +00:00
Jim Grosbach
b6aed508e3 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-09 18:37:27 +00:00
Eli Friedman
64a17b309d Make sure to handle the case where emitPredicateMatch returns false. Noticed by inspection. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139317 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 21:00:31 +00:00
Caitlin Sadowski
5d97ee31bb Added LateParsed property to TableGen attributes. 
This patch was written by DeLesley Hutchins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139300 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 17:40:49 +00:00
James Molloy
0d76b19919 Fix warning on windows; use of comparison with bool argument. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139286 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 08:12:01 +00:00
Andrew Trick
22b4c819d4 Fix a use of freed string contents. 
Speculatively try to fix our windows testers with a patch I found on the internet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139279 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 05:25:49 +00:00
Andrew Trick
ed968a9a04 whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139278 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-08 05:23:14 +00:00
Jim Grosbach
f0eee6eca8 Thumb2 assembly parsing and encoding for LDRBT. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 23:39:14 +00:00
Jim Grosbach
a8307dd1c9 Thumb2 parsing and encoding for LDR(immediate). 
The immediate offset of the non-writeback i8 form (encoding T4) allows
negative offsets only. The positive offset form of the encoding is the
LDRT instruction. Immediate offsets in the range [0,255] use encoding T3
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139254 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 20:58:57 +00:00
James Molloy
a5d5856854 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 19:42:28 +00:00
Joerg Sonnenberger
08708c8ef3 Dependency should be on the output file name, not the dependency file 
name.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-07 02:12:03 +00:00
Benjamin Kramer
e4553af561 valgrind: Suppress glibc's optiized strcasecmp harder. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139084 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-03 17:59:31 +00:00
Andrew Trick
7a15a9ad97 Attempt to silence known valgrind errors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 22:59:34 +00:00
David Greene
011dca7fac Make RecordVal Name an Init 
Store a RecordVal's name as an Init to allow class-qualified Record
members to reference Records that have Init names.  We'll use this to
provide more programmability in how we name defs and their associated
members.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139031 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 20:12:07 +00:00
Kevin Enderby
98f213cd60 Fix the disassembly of the X86 "crc32w %ax, %eax" instruction. Bug 10702. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139014 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 18:03:03 +00:00
Craig Topper
5ffedb9352 Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138997 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-02 04:17:54 +00:00
James Molloy
c047dcade5 Fix up r137380 based on post-commit review by Jim Grosbach. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138948 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-09-01 18:02:14 +00:00
NAKAMURA Takumi
bbbc283d86 lit: Normalize pathsep slashes also on %T. 
On Python-w32 with mingw msys bash, %T was replaced to "x:\foo\bar...". msys bash cannot handle DOSish paths.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138852 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-31 03:56:17 +00:00
Evan Cheng
37fefc20d3 Follow up to r138791. 
Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to
call a target hook to adjust the instruction. For ARM, this is used to
adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC
instructions have implicit def of CPSR (required since it now uses CPSR physical
register dependency rather than "glue"). If the carry flag is used, then the
target hook will *fill in* the optional operand with CPSR. Otherwise, the hook
will remove the CPSR implicit def from the MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138810 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 19:09:48 +00:00
Andrew Trick
7c12837916 Lit option for ignoring stderr output. 
This is useful for testing a build a temporarily hand instrumented
build.
Patch by arrowdodger!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138804 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 17:42:33 +00:00
Craig Topper
3daa5c29d4 Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138795 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-30 07:09:35 +00:00
Kevin Enderby
fff64ca9cf Fix the disassembly of the X86 crc32 instruction. Bug 10702 and rdar://8795217 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138771 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-29 22:06:28 +00:00
Andrew Trick
d326d3b3ef Reverted r138652, valgrind doesn't understand obj:*/tblgen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138703 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-27 06:17:30 +00:00
Owen Anderson
f1eab597b2 Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 23:32:08 +00:00
Andrew Trick
ae5ea6cab0 valgrind: Always suppress tblgen leaks. 
I'll clean up the rest of the XFAIL: vg_leak lines if this works.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138652 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 20:41:20 +00:00
Douglas Gregor
0f9d34c71d lit: Add %T as a replacement for the output directory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138640 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-26 19:05:18 +00:00
Craig Topper
113061d39b Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138552 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-25 07:42:00 +00:00
Jim Grosbach
72f39f8436 Thumb parsing and encoding support for ADD SP instructions. 
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-08-24 21:22:15 +00:00