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37 Commits

Author SHA1 Message Date
Kevin Qin
7582d8d76f [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point zero in asm parser. 
For FCMEQ, FCMGE, FCMGT, FCMLE and FCMLT, floating point zero will be
printed as #0.0 instead of #0. To support the history codes using #0,
we consider to let asm parser accept both #0.0 and #0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199621 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-20 02:14:05 +00:00
Chad Rosier
9fef0370c5 [AArch64] Add support for NEON scalar floating-point absolute difference. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195803 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 01:45:58 +00:00
Chad Rosier
48f115aabf [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-26 22:17:37 +00:00
Hao Liu
36c7806f4e Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 02:17:05 +00:00
Kevin Qin
282a979ddd implement MC layer of AArch64 neon instruction PMULL and PMULL2 with 128 bit integer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-19 01:40:25 +00:00
Kevin Qin
a08063a000 Implement aarch64 neon instruction class SIMD misc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194656 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 02:44:13 +00:00
Jiangning Liu
082ac99cc8 Implement AArch64 NEON instruction set AdvSIMD (table). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194648 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-14 01:57:32 +00:00
Chad Rosier
13c83a2a09 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-12 19:13:08 +00:00
Chad Rosier
30b2a19f3b [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 18:04:07 +00:00
Jiangning Liu
8458f371b8 Implement AArch64 Neon instruction set Perm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194123 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 03:35:27 +00:00
Jiangning Liu
258115258f Implement AArch64 Neon instruction set Bitwise Extract. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194118 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-06 02:25:49 +00:00
Jiangning Liu
3ff3a8aa75 Implement AArch64 Neon Crypto instruction classes AES, SHA, and 3 SHA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194085 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 17:42:05 +00:00
Hao Liu
591c2f738a Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194043 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-05 03:39:32 +00:00
Chad Rosier
1a035dd6df [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193816 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 22:36:59 +00:00
Chad Rosier
f7ba489730 [AArch64] Add diagnostic tests for NEON scalar shift immediate instructions (see: r193790). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193798 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 20:11:32 +00:00
Chad Rosier
1d28917dc3 [AArch64] Add support for NEON scalar shift immediate instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-31 19:28:44 +00:00
Chad Rosier
f853a034a1 [AArch64] Add support for NEON scalar floating-point compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193691 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-30 15:19:37 +00:00
Chad Rosier
c439c205ba [AArch64] Add support for NEON scalar extract narrow instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192970 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-18 14:03:24 +00:00
Chad Rosier
3b370a2ac4 [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-17 18:12:29 +00:00
Chad Rosier
dceac4c5a6 [AArch64] Add support for NEON scalar negate instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192843 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 21:04:39 +00:00
Chad Rosier
a249914462 [AArch64] Add support for NEON scalar absolute value instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192842 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 21:04:34 +00:00
Chad Rosier
8225b23c6a Update comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192806 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 16:30:10 +00:00
Chad Rosier
a2cd42a0a7 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192800 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-16 16:09:02 +00:00
Chad Rosier
942827b113 [AArch64] Add support for NEON scalar integer compare instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192596 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-14 14:37:20 +00:00
Kevin Qin
767f816b92 Implement aarch64 neon instruction set AdvSIMD (copy). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-11 02:33:55 +00:00
Hao Liu
6a5a667517 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 17:00:52 +00:00
Rafael Espindola
812ddcc50f Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." 
This reverts commit r192352. It broke the build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 15:15:17 +00:00
Hao Liu
d622bef31d Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). 
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-10 15:01:24 +00:00
Chad Rosier
c976500793 [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-08 22:09:04 +00:00
Chad Rosier
2aeb4771a6 [AArch64] Add support for NEON scalar arithmetic instructions: 
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-07 16:36:15 +00:00
Jiangning Liu
beb6afa843 Implement aarch64 neon instruction set AdvSIMD (Across). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-05 08:22:10 +00:00
Jiangning Liu
dd518bcc9d Implement aarch64 neon instruction set AdvSIMD (3V elem). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191944 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-04 09:20:44 +00:00
Jiangning Liu
477fc628b3 Initial support for Neon scalar instructions. 
Patch by Ana Pazos.

1.Added support for v1ix and v1fx types.
2.Added Scalar Pairwise Reduce instructions.
3.Added initial implementation of Scalar Arithmetic instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191263 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-24 02:47:27 +00:00
Jiangning Liu
959cd8f49b Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions, 
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-09 02:20:27 +00:00
Hao Liu
19fdc268c3 Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions: 
sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll
 and 4 convert instructions:
      scvtf,ucvtf,fcvtzs,fcvtzu


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 09:28:24 +00:00
Hao Liu
d9767021f8 Clang and AArch64 backend patches to support shll/shl and vmovl instructions and ACLE functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-15 08:26:11 +00:00
Tim Northover
87773c318f AArch64: add initial NEON support 
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-01 09:20:35 +00:00