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144 Commits

Author SHA1 Message Date
Tom Stellard
d0da9ebb0a R600/SI: Don't set isCodeGenOnly = 1 on all instructions 
We only need to set this on pseudo instructions which won't
be used by the assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229689 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 16:08:17 +00:00
Matt Arsenault
b1beec140e R600: Fix operand encoding error 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229609 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-18 02:10:42 +00:00
Matt Arsenault
8a44761afe R600/SI: Implement correct f64 fdiv 
This version passes the OpenCL conformance test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229239 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-02-14 04:30:08 +00:00
Eric Christopher
0def30471a Reuse a bunch of cached subtargets and remove getSubtarget calls 
without a Function argument.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227638 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-30 23:24:40 +00:00
Matt Arsenault
305228cc0b R600/SI: Custom lower fround 
This fixes it for SI. It also removes the pattern
used previously for Evergreen for f32. I'm not sure
if the the new R600 output is better or not, but it uses
1 fewer instructions if BFI is available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226682 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-21 18:18:25 +00:00
Matt Arsenault
8651adfe4f R600/SI: Use unordered not equal instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224065 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-12-11 22:15:35 +00:00
Craig Topper
c0dae440e6 Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222801 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-26 00:46:26 +00:00
Tom Stellard
19cb35b4bc R600/SI: Start implementing an assembler 
This was done using the Sparc and PowerPC AsmParsers as guides.  So far it
is very simple and only supports sopp instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221994 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-14 14:08:00 +00:00
Matt Arsenault
6f485c0bc5 R600/SI: Fix fmin_legacy / fmax_legacy matching for SI 
select_cc is expanded on SI, so this was never matched.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221941 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-13 23:03:09 +00:00
Matt Arsenault
b6c9c729dd R600: Don't unnecessarily repeat the register class 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221119 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-11-02 23:46:59 +00:00
Jan Vesely
787e3ca6a4 R600: FMA is VecALU only instruction 
Reviewed-by: Tom Stellard <tom@stellard.net>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219704 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-10-14 18:52:04 +00:00
Jan Vesely
286f644bce R600: Fix FROUND 
round halfway cases away from zero

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <tom@stellard.net>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217250 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-09-05 14:26:54 +00:00
Matt Arsenault
855a7e6eff R600: Add FMA instructions for Evergreen 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213882 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-24 17:41:01 +00:00
Matt Arsenault
de929f8b7d R600: Match rcp node on pre-SI 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213844 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-24 06:59:24 +00:00
Marek Olsak
4071d6f58b R600/SI: fix shadow mapping for 1D and 2D array textures 
It was conflicting with def TEX_SHADOW_ARRAY, which also handles them.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212829 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-07-11 17:11:39 +00:00
Matt Arsenault
95eb45c5d9 R600: Fix inconsistency in rsq instructions. 
R600 was using a clamped version of rsq, but SI was not. Add a
new rsq_clamped intrinsic and use them consistently.

It's unclear to me from the documentation what behavior
the R600 instructions have, so I assume they have the legacy behavior
described by the SI documents. For R600, use RECIPSQRT_IEEE
for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also
has RECIPSQRT_FF, which I'm not sure how it fits in here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211637 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-24 22:13:39 +00:00
Tom Stellard
61d64acd0c R600/SI: Add a pattern for f32 ftrunc 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211377 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-20 17:06:09 +00:00
Matt Arsenault
d9b35435b8 R600/SI: Add intrinsics for various math instructions. 
These will be used for custom lowering and for library
implementations of various math functions, so it's useful
to expose these as builtins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211247 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-19 01:19:19 +00:00
Tom Stellard
f56e7678d1 R600: Use LDS and vectors for private memory 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211110 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-17 16:53:14 +00:00
Tom Stellard
61bc72e9ae R600: Remove AMDIL instruction and register definitions 
Most of these are no longer used any more.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210915 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-13 16:38:59 +00:00
Tom Stellard
beef5c58d7 R600: Set correct InstrItinClass for instructions using *Helper classes 
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210703 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-06-11 20:51:42 +00:00
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:20 +00:00
Tom Stellard
9958475129 R600: Reorganize tablegen instruction definitions 
Each GPU family now has its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204615 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 16:07:25 +00:00
Matt Arsenault
2683baa8ac R600: Match sign_extend_inreg to BFE instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204072 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-17 18:58:11 +00:00
Tom Stellard
47feea0802 R600: LDS instructions shouldn't implicitly define OQAP 
LDS instructions are pseudo instructions which model
the OQAP defs and uses within a single instruction.

This fixes a hang in the opencv MedianFilter tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203818 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-13 17:13:04 +00:00
Matt Arsenault
3f19b69b01 R600: Remove unnecessary build_vector pattern. 
It is already fully handled in AMDGPUISelDAGToDAG.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202312 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-02-26 23:00:58 +00:00
Alp Toker
ae43cab6ba Fix known typos 
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200018 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-24 17:20:08 +00:00
Tom Stellard
35f321dde5 R600: Disable the BFE pattern 
This pattern uses an SDNodeXForm, which isn't being emitted for some
reason.  I can get it to work by attaching the PatLeaf that has the
XForm to the argument in the output pattern, but this results in an
immediate being used in a register operand, which the backend can't
handle yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199918 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-23 18:49:33 +00:00
Tom Stellard
39210ac1c6 R600: Add some missing CF instruction definitions to the .td files. 
reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199841 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 21:55:44 +00:00
Tom Stellard
f2194d3ab3 R600: CF_PUSH is the same on Evergreen and Cayman 
reviewed-by: Vincent Lejeune <vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199839 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 21:55:41 +00:00
Tom Stellard
b1d24c51fc R600: MOVA is vector only 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199827 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-01-22 19:24:24 +00:00
Tom Stellard
37ee312f77 R600: Allow ftrunc 
v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc
v3: move ftrunc pattern next to TRUNC definition, it's available since R600

Patch By: Jan Vesely

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-20 05:11:55 +00:00
Vincent Lejeune
7043c7a35e R600: Workaround for cayman loop bug 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196121 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-12-02 17:29:37 +00:00
Tom Stellard
496dbfe7b9 R600: Add support for ISD::FROUND 
NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195878 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-27 21:23:20 +00:00
Tom Stellard
0f39827340 R600/SI: Fixing handling of condition codes 
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195514 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-22 23:07:58 +00:00
Tom Stellard
a2b4eb6d15 R600/SI: Add support for private address space load/store 
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-13 23:36:50 +00:00
Vincent Lejeune
70a7d5ddb4 R600: Use function inputs to represent data stored in gpr 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-11-11 22:10:24 +00:00
Vincent Lejeune
6639f066e1 R600: Clear the VPM bit of export instructions. 
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192552 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-13 17:55:57 +00:00
Vincent Lejeune
a2f1317f09 R600: Add a ldptr intrinsic to support MSAA. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-02 16:00:33 +00:00
Vincent Lejeune
dfef7cbfc6 R600: add a pass that merges clauses. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:58 +00:00
Vincent Lejeune
5b00e833fa R600: Enable -verify-machineinstrs in some tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-10-01 19:32:38 +00:00
Tom Stellard
9c598cfebc R600: Fix handling of NAN in comparison instructions 
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191603 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-28 02:50:50 +00:00
Tom Stellard
12d43f9baf SelectionDAG: Try to expand all condition codes using getCCSwappedOperands() 
This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.

There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191601 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-28 02:50:38 +00:00
Aaron Watry
546dcc5ddc R600: Add support for LDS atomic subtract 
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 20:17:42 +00:00
Tom Stellard
79916948e1 R600: Add support for local memory atomic add 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190080 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-05 18:38:09 +00:00
Vincent Lejeune
b3df27d440 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189979 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-04 19:53:30 +00:00
Tom Stellard
a01cdea9c6 R600: Add support for i8 and i16 local memory loads 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189225 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:59 +00:00
Tom Stellard
8e78012457 R600: Add support for i8 and i16 local memory stores 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-26 15:05:49 +00:00
Tom Stellard
ec484277dd R600: Add support for i16 and i8 global stores 
Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-08-16 01:12:06 +00:00