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5 Commits

Author SHA1 Message Date
Kai Nacke
fa4d8baf54 [mips] Add registers and ALL check prefix to octeon test case. 
No functional change.

Reviewed by D. Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226574 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 16:14:02 +00:00
Kai Nacke
57e80129b9 [mips] Add octeon branch instructions bbit0/bbit032/bbit1/bbit132 
This commits adds the octeon branch instructions bbit0/bbit032/bbit1/bbit132.
It also includes patterns for instruction selection and test cases.

Reviewed by D. Sanders


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226573 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-20 16:10:51 +00:00
Kai Nacke
92e28620d3 [mips] Refine octeon instructions seq/seqi/sne/snei 
This commit refines the pattern for the octeon seq/seqi/sne/snei instructions.
The target register is set to 0 or 1 according to the result of the comparison.
In C, this is something like

rd = (unsigned long)(rs == rt)

This commit adds a zext to bring the result to i64. With this change the
instruction is selected for this type of code. (gcc produces the same code for
the above C code.)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225968 91177308-0d34-0410-b5e6-96231b3b80d8
 2015-01-14 10:19:09 +00:00
Kai Nacke
b96fc4a5ea [mips] Add more Octeon cnMips instructions 
Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205449 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-02 18:40:43 +00:00
Kai Nacke
ebf9f0c6cb [MIPS] Add cpu octeon and some instructions 
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204337 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-20 11:51:58 +00:00