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189 Commits

Author SHA1 Message Date
Jim Grosbach
1d6111c5ac Kill of the vestiges of the 'call' Modifier (no longer needed for PLT). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 21:36:43 +00:00
Evan Cheng
a0792de66c - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This 
allow target to correctly compute latency for cases where static scheduling
  itineraries isn't sufficient. e.g. variable_ops instructions such as
  ARM::ldm.
  This also allows target without scheduling itineraries to compute operand
  latencies. e.g. X86 can return (approximated) latencies for high latency
  instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
  e.g. ldm and those used by store multiple instructions, e.g. stm.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115755 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-06 06:27:31 +00:00
Jim Grosbach
78890f41f4 Nuke the rest of the :comment references 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115373 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-01 23:21:38 +00:00
Jim Grosbach
a3fbadfcd8 Nuke a few more unused asm strings 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115193 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 19:53:58 +00:00
Jim Grosbach
71d933a49e The asm strings are never used at all, so just nuke 'em entirely. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115160 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 16:56:53 +00:00
Jim Grosbach
7ebc863c15 Go ahead and jump! 
Now that the MC lowering handles the expansion of the pseudos, kill the horrible
blobs of text.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115130 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 02:18:06 +00:00
Evan Cheng
0e55fd61ae ARM instruction itinerary fixes: 
1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115121 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-30 01:08:25 +00:00
Evan Cheng
5d42c567c9 Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115010 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 00:49:25 +00:00
Evan Cheng
7e1bf305cf Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-29 00:27:46 +00:00
Owen Anderson
f523e476c2 Revert r114703 and r114702, removing the isConditionalMove flag from instructions. After further 
reflection, this isn't going to achieve the purpose I intended it for.  Back to the drawing board!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 23:45:25 +00:00
Owen Anderson
71e416ac3a Add isConditionalMove bits to X86 and ARM instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114703 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 22:57:01 +00:00
Jim Grosbach
2e6ae13bf6 Clean up the 'trap' instruction printing a bit. Non-Darwin assemblers don't 
(yet) recognize the 'trap' mnemonic, so we use .short/.long to emit the
opcode directly. On Darwin, however, we do want the mnemonic for more
readable assembly code and better disassembly.

Adjust the .td file to use the 'trap' mnemonic and handle using the binutils
workaround in the assembly printer. Also tweak the formatting of the opcode
values to make them consistent between the MC printer and the old printer.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114679 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-23 18:05:37 +00:00
Gabor Greif
f7d10f5c12 set isCompare for another three Thumb1 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 22:00:50 +00:00
Gabor Greif
007248b478 set comparable for a bunch of Thumb instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113849 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 20:47:43 +00:00
Evan Cheng
5f54ce3473 For each instruction itinerary class, specify the number of micro-ops each 
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-09 18:18:55 +00:00
Jim Grosbach
e2f70d1724 grammar tweak 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113289 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-07 21:30:25 +00:00
Jim Grosbach
663e339e20 Make ARM add rN, sp, #imm instructions rematerializable. That's how the address of locals is calculated, so this should 
help relieve register pressure a bit. Recalculating the local address is
almost always going to be better than spilling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112503 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-30 19:49:58 +00:00
Evan Cheng
5818032521 Delete some unused instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110710 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-08-10 19:36:22 +00:00
Bob Wilson
d4d188e502 Move newlines before inline jumptables from the asm strings in .td files to 
the jtblock_operand print methods.  This avoids extra newlines in the
disassembler's output.  PR7757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109948 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-07-31 06:28:10 +00:00
Jim Grosbach
a967d1121a LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it 
being moved around away from the jump table it references. rdar://8104340

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-21 21:27:27 +00:00
Jim Grosbach
18f30e6f5e Clean up 80 column violations. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-06-02 21:53:11 +00:00
Jim Grosbach
c9792a3c1f Cosmetic cleanup. No functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:51:20 +00:00
Jim Grosbach
5caeff5c01 make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-28 17:37:40 +00:00
Jim Grosbach
0798eddd07 Update the saved stack pointer in the sjlj function context following either 
an alloca() or an llvm.stackrestore(). rdar://8031573



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-27 23:49:24 +00:00
Jim Grosbach
54e13eceff fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-26 01:22:21 +00:00
Jim Grosbach
5eb1951539 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-22 01:06:18 +00:00
Evan Cheng
9085f98b32 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104115 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 07:28:01 +00:00
Evan Cheng
5fd1c9be2d Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104111 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 06:07:03 +00:00
Evan Cheng
ea420b20d4 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104102 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-19 01:52:25 +00:00
Bob Wilson
7f43fd84db Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. 
Obvious in retrospect but not fun to debug.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103969 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-17 20:31:13 +00:00
Anton Korobeynikov
bd91ea53f8 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-16 09:15:36 +00:00
Anton Korobeynikov
418d1d954d "trap" pseudo-op turned out to be apple-local. 
Temporary emit it as raw bytes until it will be added to binutils as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-15 17:19:20 +00:00
Evan Cheng
fb3611daad Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-11 07:26:32 +00:00
Chris Lattner
60e9eac357 set SDNPVariadic on nodes throughout the rest of the targets that 
need them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-19 05:33:51 +00:00
Bob Wilson
ab3460519e Remove the writeback flag from ARM's address mode 4. Now that we have separate 
instructions for ld/st with writeback, the flag is completely redundant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98643 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-16 17:46:45 +00:00
Bob Wilson
815baebe1c Change ARM ld/st multiple instructions to have variant instructions for 
writebacks to the address register.  This gets rid of the hack that the
first register on the list was the magic writeback register operand.  There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand.  The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other.  This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-13 01:08:20 +00:00
Johnny Chen
dd0f3cf189 Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero 
operands into their own PrintMethod, in order not to pollute the printOperand()
impl with disassembly only Imm modifiers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98172 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-10 18:59:38 +00:00
Johnny Chen
cb721da4c6 Modified the asm string of 16-bit Thumb MUL instruction so that it prints: 
MULS <Rdm>, <Rn>, <Rdm>

according to A8.6.105 MUL Encoding T1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97675 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 23:15:43 +00:00
Johnny Chen
93042d1dc8 Added 32-bit Thumb instructions: CPS, SDIV, UDIV, SXTB16, SXTAB16, UXTAB16, SEL, 
SMMULR, SMMLAR, SMMLSR, TBB, TBH, and 16-bit Thumb instruction CPS for
disassembly only.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97573 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-02 18:14:57 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 23:47:46 +00:00
Johnny Chen
d86d269f08 Added the following 16-bit Thumb instructions for disassembly only: YIELD, WFE, 
WFI, SEV, SETEND.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97149 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-25 17:51:03 +00:00
Johnny Chen
bd2c623903 Added tNOP for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97105 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-25 03:28:51 +00:00
Johnny Chen
4c61cdd307 Added tSVC and tTRAP for disassembly only. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97098 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-25 02:21:11 +00:00
Jim Grosbach
4642ad3af1 Updated version of r96634 (which was reverted due to failing 176.gcc and 
126.gcc nightly tests. These failures uncovered latent bugs that machine DCE
could remove one half of a stack adjust down/up pair, causing PEI to assert.
This update fixes that, and the tests now pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96822 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-22 23:10:38 +00:00
Jim Grosbach
80dc116ce3 80 column cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96393 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:23:02 +00:00
Jim Grosbach
6417171026 Remove trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-16 21:07:46 +00:00
Johnny Chen
c6f7b27fda Added BKPT/tBKPT (breakpoint) to the instruction table for disassembly purpose. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 18:12:29 +00:00
Jim Grosbach
4152778605 Radar 7417921 
tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95686 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-09 19:51:37 +00:00
Jim Grosbach
a87ded2695 tighten up eh.setjmp sequence a bit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-08 23:22:00 +00:00
Jim Grosbach
c90a153ad0 Adjust setjmp instruction sequence to not need 32-bit alignment padding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94627 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-27 00:07:20 +00:00