31452 Commits

Author SHA1 Message Date
Jozef Kolek
13fbabb7c8 [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222900 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 18:18:42 +00:00
Daniel Sanders
68de93c3b4 [mips] Add synci instruction.
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222899 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 17:28:10 +00:00
Jozef Kolek
2b8e58cc82 [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
Differential Revision: http://reviews.llvm.org/D6419


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222887 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 14:41:44 +00:00
Charlie Turner
72ba1af89c Stop uppercasing build attribute data.
The string data for string-valued build attributes were being unconditionally
uppercased. There is no mention in the ARM ABI addenda about case conventions,
so it's technically implementation defined as to whether the data are
capitialised in some way or not. However, there are good reasons not to
captialise the data.

  * It's less work.
  * Some vendors may legitimately have case-sensitive checks for these
    attributes which would fail on LLVM generated object files.
  * There could be locale issues with uppercasing.

The original reasons for uppercasing appear to have stemmed from an
old codesourcery toolchain behaviour, see

http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/87133

This patch makes the object file emitted no longer captialise string
data, it encodes as seen in the assembly source.

Change-Id: Ibe20dd6e60d2773d57ff72a78470839033aa5538

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222882 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-27 12:13:56 +00:00
Matt Arsenault
b69378a26d R600/SI: Use ZeroOrNegativeOneBooleanContent
This sort of doesn't matter since the setcc type is i1, but
this previously was using the default UndefinedBooleanContent. This
makes it more consistent with R600. This enables more optimizations
which typically give up on UndefinedBooleanContent. For example,
there is already a special case target DAG combine for
setcc + sext which can be eliminated in favor of what the generic
DAG combiner can do if it assumes boolean values are sign extended.
Since -1 is an inline immediate, using it is basically free and the
backend already uses it when a boolean value is needed in a wider type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222850 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 21:23:15 +00:00
Colin LeMahieu
74eb264493 [Hexagon] Adding cmp* immediate form instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222849 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 19:43:12 +00:00
Jozef Kolek
832e2301cd [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
Differential Revision: http://reviews.llvm.org/D6405


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222847 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 18:56:38 +00:00
Colin LeMahieu
1df05cd7b6 [Hexagon] Adding and64, or64, and xor64 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222846 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 18:55:59 +00:00
Matt Arsenault
f87cce1540 R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies
This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222844 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 18:18:28 +00:00
Will Newton
87a2f3751c Update AArch64 ELF relocations to ABI 1.0
This mostly entails adding relocations, however there are a couple of
changes to existing relocations:

1. R_AARCH64_NONE is defined to be zero rather than 256

R_AARCH64_NONE has been defined to be zero for a long time elsewhere
e.g. binutils and glibc since the submission of the AArch64 port in
2012 so this is required for compatibility.

2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21

I don't think there is any way for relocation names to leak out of LLVM
so this should not break anything.

Tested with check-all with no regressions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222821 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 10:49:18 +00:00
Elena Demikhovsky
10c8f38047 AVX-512: Scalar ERI intrinsics
including SAE mode and memory operand.
Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future.

The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect.
I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction.

http://reviews.llvm.org/D6378



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222820 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 10:46:49 +00:00
Craig Topper
c0dae440e6 Replace neverHasSideEffects=1 with hasSideEffects=0 in all .td files.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222801 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-26 00:46:26 +00:00
Simon Pilgrim
7f6cee9626 [X86][SSE] Improvements to byte shift shuffle matching
Since (v)pslldq / (v)psrldq instructions resolve to a single input argument it is useful to match it much earlier than we currently do - this prevents more complicated shuffles (notably insertion into a zero vector) matching before it.

Differential Revision: http://reviews.llvm.org/D6409



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222796 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 22:34:59 +00:00
Colin LeMahieu
5bf7bcf6b3 [Hexagon] Adding add64 and sub64 instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222795 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 22:15:44 +00:00
Colin LeMahieu
7c45f13db6 Reverting 222792
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222793 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 21:39:57 +00:00
Colin LeMahieu
9980f8c78d [Hexagon] Adding compare with immediate instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222792 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 21:30:28 +00:00
Colin LeMahieu
c688fdbeea [Hexagon] Adding NOP encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222791 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 21:23:07 +00:00
Matt Arsenault
c9d99b504d R600/SI: Only use one DEBUG()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222789 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 21:03:22 +00:00
Cameron McInally
9f4bb0420d [AVX512] Add 512b integer shift by variable intrinsics and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222786 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 20:41:51 +00:00
Colin LeMahieu
609c7fa14e [Hexagon] Adding C2_mux instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222784 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 20:20:09 +00:00
Craig Topper
690b96281f Remove space before tab in all AVX512 mnemonic strings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222778 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 20:11:23 +00:00
Colin LeMahieu
a95af5c17d [Hexagon] Replacing cmp* instructions with ones that contain encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222771 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 18:20:52 +00:00
Chandler Carruth
d8022cd7d4 Revert r222746: That commit did not update any tests and caused two R600
tests to start failing.

Original commit log: R600/SI: Disable commutativity for MIN/MAX_LEGACY

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 10:50:41 +00:00
Zoran Jovanovic
137c475805 [mips][micromips] Use call instructions with short delay slots
Differential Revision: http://reviews.llvm.org/D6338


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 10:50:00 +00:00
Marek Olsak
0ab565a275 R600/SI: Disable commutativity for MIN/MAX_LEGACY
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222746 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 09:49:23 +00:00
Matt Arsenault
87926dfe7e R600/SI: Fix allocating flat_scr_lo / flat_scr_hi
Only the super register flat_scr was marked as reserved,
so in some cases with high register usage it would still
try to allocate the subregisters.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222737 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 07:53:06 +00:00
Juergen Ributzka
a4ebd338c4 [FastISel][AArch64] Fix and extend the tbz/tbnz pattern matching.
The pattern matching failed to recognize all instances of "-1", because when
comparing against "-1" we didn't use an APInt of the same bitwidth.

This commit fixes this and also adds inverse versions of the conditon to catch
more cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222722 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 04:16:15 +00:00
Hal Finkel
b932ed3c3d [PowerPC] Add the 'attn' instruction
The attn instruction is not part of the Power ISA, but is documented in the A2
user manual, and is accepted by the GNU assembler for the A2 and the POWER4+.
Reported as part of PR21650.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222712 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-25 00:30:11 +00:00
Hal Finkel
5d6f185653 [PowerPC] Implement combineRepeatedFPDivisors
This does not matter on newer cores (where we can use reciprocal estimates in
fast-math mode anyway), but for older cores this allows us to generate better
fast-math code where we have multiple FDIVs with a common divisor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222710 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 23:45:21 +00:00
Chad Rosier
6b3c567613 [AArch64] Fix clobber computation in A57LoadBalancing pass.
Extremely difficult to reproduce, so no test case included.
PR21637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222677 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:57:58 +00:00
Colin LeMahieu
5a6b6744c0 Removing unused variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222676 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:55:32 +00:00
Ulrich Weigand
edc6a13992 [PowerPC] Fix PR 21652 - copy st_other bits on symbol assignment
When processing an assignment in the integrated assembler that sets
a symbol to the value of another symbol, we need to copy the st_other
bits that encode the local entry point offset.

Modeled after MipsTargetELFStreamer::emitAssignment handling of the
ELF::STO_MIPS_MICROMIPS flag.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222672 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:09:47 +00:00
Colin LeMahieu
5de3458c18 [Hexagon] Adding asrh instruction, removing unused multiclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 18:04:42 +00:00
Colin LeMahieu
c1c7be0928 [Hexagon] Adding aslh instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222668 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 17:44:19 +00:00
Colin LeMahieu
f309d8ee65 [Hexagon] Adding zxth instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 17:11:34 +00:00
Colin LeMahieu
a723df08bb [Hexagon] Adding zxtb instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222660 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:48:43 +00:00
Jozef Kolek
c19526770e [mips][microMIPS] Fix JRADDIUSP instruction
Fix JRADDIUSP instruction, remove delay slot flag because this instruction
doesn't have delay slot.

Differential Revision: http://reviews.llvm.org/D6365


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 16:14:10 +00:00
Jozef Kolek
b955bed064 [mips][microMIPS] Implement LBU16, LHU16, LW16, SB16, SH16 and SW16 instructions
Differential Revision: http://reviews.llvm.org/D5122


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222653 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:39:13 +00:00
Jozef Kolek
d49e74eaa5 [mips][microMIPS] Implement 16-bit instructions registers including ZERO instead of S0
Implement microMIPS 16-bit instructions register set: $0, $2-$7 and $17.

Differential Revision: http://reviews.llvm.org/D5780


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222652 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:25:53 +00:00
Aaron Ballman
8d6f6a27c7 Removing a variable that is initialized but never read. The original author has been alerted to the warning, in case this variable is meant to be used. Fixes -Werror builds in the meantime.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 14:03:16 +00:00
Jozef Kolek
18700de8fc [mips][microMIPS] Implement disassembler support for 16-bit instructions
With the help of new method readInstruction16() two bytes are read and
decodeInstruction() is called with DecoderTableMicroMips16, if this fails
four bytes are read and decodeInstruction() is called with
DecoderTableMicroMips32.

Differential Revision: http://reviews.llvm.org/D6149


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 13:29:59 +00:00
Andrea Di Biagio
a1e1f01699 [X86] Improved target specific combine on VSELECT dag nodes.
This patch teaches function 'transformVSELECTtoBlendVECTOR_SHUFFLE' how to
convert VSELECT dag nodes to shuffles on targets that do not have SSE4.1.
On pre-SSE4.1 targets, we can still perform blend operations using movss/movsd.

Also, removed a target specific combine that performed a premature lowering of
VSELECT nodes to target specific MOVSS/MOVSD nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222647 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-24 12:23:15 +00:00
Michael Kuperstein
d539147834 [X86] Fixes bug in build_vector v4x32 lowering
r222375 made some improvements to build_vector lowering of v4x32 and v4xf32 into an insertps, but it missed a case where:

1. A single extracted element is used twice.
2. The lower of the two non-zero indexes should be preserved, and the higher should be used for the dest mask.

This caused a crash, since the source value for the insertps ends-up uninitialized.

Differential Revision: http://reviews.llvm.org/D6377

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 13:09:06 +00:00
Craig Topper
71777d18ad Add missing override keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 09:40:13 +00:00
Elena Demikhovsky
ae1ae2c3a1 Masked Vector Load and Store Intrinsics.
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.
Added SDNodes for masked operations and lowering patterns for X86 code generator.
Examples:
<16 x i32> @llvm.masked.load.v16i32(i8* %addr, <16 x i32> %passthru, i32 4 /* align */, <16 x i1> %mask)
declare void @llvm.masked.store.v8f64(i8* %addr, <8 x double> %value, i32 4, <8 x i1> %mask)

Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.

http://reviews.llvm.org/D6191



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222632 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 08:07:43 +00:00
Matt Arsenault
4f5aa5994e R600: Fix extloads of i1 on R600/Evergreen
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222631 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:54 +00:00
Matt Arsenault
716ce08250 R600: Fix assert on copy of an i1 on pre-SI
i1 is not a legal type on Evergreen, so this combine proceeded
and tried to produce a bitcast between i1 and i8.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222630 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-23 02:57:52 +00:00
Simon Pilgrim
53a43d38df Tidied up target triple OS detection. NFC
Use Triple::isOS*() helper functions where possible.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222622 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 19:12:10 +00:00
Chandler Carruth
e915b4b7c8 [x86] Teach the vector shuffle yet another step of canonicalization.
No functionality changed yet, but this will prevent subsequent patches
from having to handle permutations of various interleaved shuffle
patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222614 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-22 09:18:53 +00:00
Joerg Sonnenberger
0b1407b5cf Fix transformation of add with pc argument to adr for non-immediate
arguments.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222587 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-21 22:39:34 +00:00