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3590 Commits

Author SHA1 Message Date
Jakub Staszak
f55c1c8588 Rename BlockFrequency to BlockFrequencyInfo and MachineBlockFrequency to 
MachineBlockFrequencyInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135937 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-25 19:25:40 +00:00
Bill Wendling
1359c6d718 Add a method to set the compact unwind info. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135806 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 21:17:05 +00:00
Jakub Staszak
23f34f1c22 Allow getBlockFreq to return 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-22 02:24:57 +00:00
Evan Cheng
203576aa0c Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc. 
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 19:50:42 +00:00
Evan Cheng
e76a33b956 Add MCObjectFileInfo and sink the MCSections initialization code from 
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135569 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-20 05:58:47 +00:00
Devang Patel
497a397f3e Revert r135423. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135454 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 00:28:24 +00:00
Bill Wendling
7d36534d22 Rename CompactEncoding to CompactUnwindEncoding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135448 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-19 00:00:58 +00:00
Bill Wendling
a67dcea072 Move the compact encoding from the target-specific library to the code-gen 
library.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135443 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 23:38:40 +00:00
Evan Cheng
2d28617de2 Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for 
better location welcome).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 22:29:13 +00:00
Evan Cheng
0e6a052331 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 20:57:22 +00:00
Devang Patel
1360bc8eb0 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
[take 2]


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135423 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 20:55:23 +00:00
Chris Lattner
db125cfaf5 land David Blaikie's patch to de-constify Type, with a few tweaks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-18 04:54:35 +00:00
Jakub Staszak
59a9dab4d8 Add MachineBlockFrequency analysis. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135352 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-16 20:23:20 +00:00
Jakob Stoklund Olesen
b4ddedce59 Extract parts of RAGreedy::splitAroundRegion as SplitKit methods. 
This gets rid of some of the gory splitting details in RAGreedy and
makes them available to future SplitKit clients.

Slightly generalize the functionality to support multi-way splitting.
Specifically, SplitEditor::splitLiveThroughBlock() supports switching
between different register intervals in a block.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-15 21:47:57 +00:00
Evan Cheng
9bc402c8d4 Fix up TargetLoweringObjectFile ctors to properly initialize fields. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135068 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 19:54:59 +00:00
Jay Foad
fc6d3a4986 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135040 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-13 10:26:04 +00:00
Jakub Staszak
687dc24e1d - Make BranchProbability constructor public. 
- Add getCompl() method.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134857 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-10 02:12:39 +00:00
Cameron Zwarich
33390848a7 Add an intrinsic and codegen support for fused multiply-accumulate. The intent 
is to use this for architectures that have a native FMA instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134742 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 21:39:21 +00:00
Jakob Stoklund Olesen
51458ed09e Be more aggressive about following hints. 
RAGreedy::tryAssign will now evict interference from the preferred
register even when another register is free.

To support this, add the EvictionCost struct that counts how many hints
are broken by an eviction. We don't want to break one hint just to
satisfy another.

Rename canEvict to shouldEvict, and add the first bit of eviction policy
that doesn't depend on spill weights: Always make room in the preferred
register as long as the evictees can be split and aren't already
assigned to their preferred register.

Also make the CSR avoidance more accurate. When looking for a cheaper
register it is OK to use a new volatile register. Only CSR aliases that
have never been used before should be avoided.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134735 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-08 20:46:18 +00:00
Lang Hames
944520f38c Add functions 'hasPredecessor' and 'hasPredecessorHelper' to SDNode. The 
hasPredecessorHelper function allows predecessors to be cached to speed up
repeated invocations. This fixes PR10186.

X.isPredecessorOf(Y) now just calls Y.hasPredecessor(X)

Y.hasPredecessor(X) calls Y.hasPredecessorHelper(X, Visited, Worklist) with
empty Visited and Worklist sets (i.e. no caching over invocations).

Y.hasPredecessorHelper(X, Visited, Worklist) caches search state in Visited
and Worklist to speed up repeated calls. The Visited set is searched for X
before going to the worklist to further search the DAG if necessary.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134592 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-07 04:31:51 +00:00
Jakob Stoklund Olesen
d519de0827 Include a source location when complaining about bad inline assembly. 
Add a MI->emitError() method that the backend can use to report errors
related to inline assembly. Call it from X86FloatingPoint.cpp when the
constraints are wrong.

This enables proper clang diagnostics from the backend:

$ clang -c pr30848.c
pr30848.c:5:12: error: Inline asm output regs must be last on the x87 stack
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
           ^
1 error generated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134307 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-07-02 03:53:34 +00:00
Rafael Espindola
cfe5254cd3 Create a isFullCopy predicate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134189 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-30 21:15:52 +00:00
Devang Patel
272511f518 Revert r133953 for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134116 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-29 23:50:13 +00:00
Evan Cheng
e837dead3c - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and 
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-28 19:10:37 +00:00
Evan Cheng
f46e7e3d7f Remove RegClass2VRegMap from MachineRegisterInfo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133967 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 23:54:40 +00:00
Evan Cheng
f10711fb8c Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc can split live ranges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133962 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 23:40:45 +00:00
Devang Patel
016c5829a5 During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133953 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-27 22:32:04 +00:00
Rafael Espindola
5b220213bf There is only one register coalescer. Merge it into the base class and 
remove the analysis group.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133899 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-26 22:34:10 +00:00
Rafael Espindola
fdf16ca44f Move RegisterCoalescer.h to lib/CodeGen. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133895 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-26 21:41:06 +00:00
Devang Patel
8594d429e0 Handle debug info for i128 constants. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133821 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-24 20:46:11 +00:00
Jay Foad
7d715dfe6d Fix a FIXME by making GlobalVariable::getInitializer() return a 
const Constant *.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133400 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-19 18:37:11 +00:00
Benjamin Kramer
22a54c1cd7 Don't allocate empty read-only SmallVectors during SelectionDAG deallocation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133348 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-18 13:13:44 +00:00
Eric Christopher
362fee90b9 Lower multiply with overflow checking to __mulo<mode> 
calls if we haven't been able to lower them any
other way.

Fixes rdar://9090077 and rdar://9210061


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133288 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-17 20:41:29 +00:00
Lang Hames
8d857660ce Add a hook for PBQP clients to run a custom pre-alloc pass to run prior to PBQP allocation. Patch by Arnaud Allard de Grandmaison. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133249 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-17 07:09:01 +00:00
Jakub Staszak
7cc2b07437 Introduce MachineBranchProbabilityInfo class, which has similar API to 
BranchProbabilityInfo (expect setEdgeWeight which is not available here).
Branch Weights are kept in MachineBasicBlocks. To turn off this analysis
set -use-mbpi=false.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133184 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 20:22:37 +00:00
Owen Anderson
23b0766b47 Fix formatting. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133164 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 16:52:24 +00:00
Owen Anderson
77b4b13c2a Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133106 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 23:35:18 +00:00
Andrew Trick
4cb971ce1c Added -stress-sched flag in the Asserts build. 
Added a test case for handling physreg aliases during pre-RA-sched.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133063 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 17:16:12 +00:00
Bruno Cardoso Lopes
9a767330f5 Add one more argument to the prefetch intrinsic to indicate whether it's a data 
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 04:58:37 +00:00
Bill Wendling
3bdc190d33 Reformatting. Moving class definitions to more natural places. No functionalogical changes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132876 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-11 11:37:49 +00:00
Cameron Zwarich
a86686e643 Provide an ARMCCState subclass of CCState so that ARM clients will always set 
CallOrPrologue correctly and eliminate the existing setter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 20:59:24 +00:00
Cameron Zwarich
a50760f43b Rename the ParmContext enum values to make a bit more sense and add a small 
comment on their meaning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132854 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 20:37:36 +00:00
Cameron Zwarich
a0f803a2e3 Remove tabs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132853 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 20:31:39 +00:00
Eric Christopher
471e422480 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 23:55:35 +00:00
Lang Hames
d0685b0e28 Switched to DenseMap for allowed sets in PBQP. Reduces total LLC time by 15% on CINT2006 for x86-32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132707 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-07 06:05:58 +00:00
Devang Patel
ee1f87881b Remove dead code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132488 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 21:31:00 +00:00
Chad Rosier
11772e093f Typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132437 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-01 23:32:40 +00:00
Charles Davis
f46337004a When generating code for Win64 EH, emit StartProc and EndProc directives. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132250 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 04:21:04 +00:00
Rafael Espindola
5b23b7fe31 Make size computation less brittle. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132222 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 22:05:41 +00:00
Charles Davis
88c816453f Add the suffix to the Win64 EH data sections' names if given. Add a test for 
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132220 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 21:38:47 +00:00