6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-24 12:29:33 +00:00
Code Issues Projects Releases Wiki Activity
65,086 Commits 39 Branches 0 Tags
Commit Graph

731 Commits

Author SHA1 Message Date
Anton Korobeynikov
e765f2b5e3 Describe what's going on with mingw alloca and why do we need separate instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97888 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-06 20:07:32 +00:00
Anton Korobeynikov
043f3c2a0e Lower dynamic stack allocation on mingw32 to separate instruction. 
We cannot use a normal call here since it has extra unmodelled side
effects (it changes stack pointer). This should fix PR5292.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97884 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-06 19:32:29 +00:00
Jakob Stoklund Olesen
3cfe01072c Fix the remaining MUL8 and DIV8 to define AX instead of AL,AH. 
These instructions technically define AL,AH, but a trick in X86ISelDAGToDAG
reads AX in order to avoid reading AH with a REX instruction.

Fix PR6489.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97742 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-04 20:42:07 +00:00
Chris Lattner
99fe641325 remove nvload and two patterns that use it which are 
better done by dag combine.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97633 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 02:14:54 +00:00
Chris Lattner
f85eff76b2 factor the 'in the default address space' check out to a single 
'dsload' pattern.  tblgen doesn't check patterns to see if they're
textually identical.  This allows better factoring.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97630 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 01:52:59 +00:00
Chris Lattner
1840991d54 factor the 'sign extended from 8 bit' patterns better so 
that they are not destination type specific.  This allows
tblgen to factor them and the type check is redundant with
what the isel does anyway.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97629 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-03-03 01:45:01 +00:00
Dan Gohman
bc9d98b52d The mayHaveSideEffects flag is no longer used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-27 23:47:46 +00:00
Jakob Stoklund Olesen
c3027f769a DIV8r must define %AX since X86DAGToDAGISel::Select() sometimes uses it 
instead of %AL/%AH.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97006 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-24 00:39:35 +00:00
Chris Lattner
6d9f86b773 remove a bunch of dead named arguments in input patterns, 
though some look dubious afaict, these are all ok.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-23 06:54:29 +00:00
Sean Callanan
cebe955779 Added the rdtscp instruction to the x86 instruction 
tables.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96073 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 02:06:11 +00:00
Sean Callanan
95a5a7d570 Fixed encodings for invlpg, invept, and invvpid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96065 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 01:48:34 +00:00
Chris Lattner
a599de2410 remove special cases for vmlaunch, vmresume, vmxoff, and swapgs 
fix swapgs to be spelled right.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-13 00:41:14 +00:00
Chris Lattner
a0331199fc enhance the immediate field encoding to know whether the immediate 
is pc relative or not, mark call and branches as pcrel.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 22:27:07 +00:00
Chris Lattner
fdfeb6976f Add support for a union type in LLVM IR. Patch by Talin! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96011 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 20:49:41 +00:00
Daniel Dunbar
ccfa1db538 X86: Fix definition for RCL/RCR.*m? operations -- they were getting represented 
with "tied memory operands", which is wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-12 01:22:03 +00:00
Chris Lattner
b8db331588 improve encoding information for branches. We now know they have 
8 or 32-bit immediates, which allows the new encoder to handle
them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95927 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 21:45:31 +00:00
Chris Lattner
8b442a814e unbreak the build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95915 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 19:52:11 +00:00
Chris Lattner
bd13fb6254 refactor the conditional jump instructions in the .td file to 
use a multipattern that generates both the 1-byte and 4-byte 
versions from the same defm


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95901 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-11 19:25:55 +00:00
Dan Gohman
f451cb870e Fix "the the" and similar typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-10 16:03:48 +00:00
David Greene
51898d7a89 TableGen fragment refactoring. 
Move some utility TableGen defs, classes, etc. into a common file so
they may be used my multiple pattern files.  We will use this for
the AVX specification to help with the transition from the current
SSE specification.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95727 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-09 23:52:19 +00:00
Chris Lattner
8f60e4d679 fix incorrect encoding of SBB8mi that Kevin noticed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95448 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 22:56:11 +00:00
Chris Lattner
35e0e84f93 teach X86MCInstLower to lower the MOV32r0 and MOV8r0 
pseudo instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 21:21:06 +00:00
Chris Lattner
c74e333ecc factor code better in X86MCInstLower::Lower, teach it to 
lower the SETB* instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95431 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-05 21:13:48 +00:00
Kevin Enderby
12ce0de462 Added support for X86 instruction prefixes so llvm-mc can assemble them. The 
Lock prefix, Repeat string operation prefixes and the Segment override prefixes.
Also added versions of the move string and store string instructions without the
repeat prefixes to X86InstrInfo.td. And finally marked the rep versions of
move/store string records in X86InstrInfo.td as isCodeGenOnly = 1 so tblgen is
happy building the disassembler files.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95252 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-02-03 21:04:42 +00:00
Evan Cheng
aa92bec010 Change TAILJMP's to be varargs and transfer implicit uses over from TCRETURN's. Otherwise the missing uses can make post-regalloc scheduling do bad things. This fixes 403.gcc. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94950 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-31 07:28:44 +00:00
Daniel Dunbar
b834f5d13d MC/X86 AsmParser: Handle absolute memory operands correctly. We were doing 
something totally broken and parsing them as immediates, but the .td file also
had the wrong match class so things sortof worked. Except, that is, that we
would parse
  movl $0, %eax
as
  movl 0, %eax
Feel free to guess how well that worked.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94869 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-30 01:02:48 +00:00
Daniel Dunbar
728e5eb927 X86.td: Refactor to bring operands that use print_pcrel_imm together. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94861 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-30 00:24:12 +00:00
Daniel Dunbar
ec2b1f1beb AsmMatcher/X86: Separate out sublass for memory operands that have no segment 
register, and use to cleanup a FIXME in X86AsmParser.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94859 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-30 00:24:00 +00:00
Evan Cheng
3bda20112e Eliminate or_not_add and just use AddedComplexity so isel tries or_is_add patterns first. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93245 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 18:31:19 +00:00
Dan Gohman
f1b4d26e67 Reapply the MOV64r0 patch, with a fix: MOV64r0 clobbers EFLAGS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93229 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-12 04:42:54 +00:00
Evan Cheng
199c4240fe Extend r93152 to work on OR r, r. If the source set bits are known not to overlap, then select as an ADD instead. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 22:03:29 +00:00
Evan Cheng
05920b8146 Revert 93158. It's breaking quite a few x86_64 tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93185 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 21:13:41 +00:00
Evan Cheng
ac000fa0ed Do not turn 8-bit OR to ADD since ADD8ri is not 3-addressfiable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93182 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 20:18:04 +00:00
Dan Gohman
71c25b7d7b Re-instate MOV64r0 and MOV16r0, with adjustments to work with the 
new AsmPrinter. This is perhaps less elegant than describing them
in terms of MOV32r0 and subreg operations, but it allows the
current register to rematerialize them.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93158 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:37:57 +00:00
Dan Gohman
7e0d64a49c Pattern top-level operators don't need to be restricted to a 
single user. The _su forms are intended for non-top-level nodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93155 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:21:05 +00:00
Evan Cheng
4b0345be30 Select an OR with immediate as an ADD if the input bits are known zero. This allow the instruction to be 3address-fied if needed. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93152 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-11 17:03:47 +00:00
Evan Cheng
b093bd0565 Fix what looks to me obvious instruction definition bugs. 
1. CMPXCHG8B and CMPXCHG16B did not specify implicit physical register defs and uses.
2. LCMPXCHG8B is loading 64 bit memory, not 32 bit.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-08 01:29:19 +00:00
Dan Gohman
4361bbfd0e Remove the SDNPAssociative properties for the flags-producing 
operators. Eli pointed out that it's not obvious what that
would mean.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92555 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-05 00:44:20 +00:00
Dan Gohman
43ffe6769a Add SDNPCommutative and SDNPAssociative to several X86 target nodes. 
This lets isel fold loads into them in more cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92506 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-01-04 20:51:05 +00:00
Eli Friedman
ba7b1c4db4 PR5886: Make sure IMUL32m is marked as setting EFLAGS, so scheduling doesn't 
do illegal stuff around it.  No testcase because the issue is very fragile.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92167 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-26 20:08:30 +00:00
Chris Lattner
ac105c4dca really remove the instruction, don't just comment it out 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91976 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:46:40 +00:00
Chris Lattner
9e3238303c completely eliminate the MOV16r0 'instruction'. The only 
interesting part of this is the divrem changes, which are
already tested by CodeGen/X86/divrem.ll.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91975 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:45:04 +00:00
Chris Lattner
6a38182471 stop pattern matching 16-bit zero's of a register to MOV16r0, 
instead use the appropriate subreggy thing.  This generates identical
code on some large apps (thanks to Evan's cross class coalescing
stuff he did back in july).  This means that MOV16r0 can go away
completely in the future soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91972 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-23 01:30:26 +00:00
Evan Cheng
b1f4981333 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-22 17:47:23 +00:00
Evan Cheng
400073d546 On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 07:40:29 +00:00
Sean Callanan
108934c65d Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-18 00:01:26 +00:00
Evan Cheng
2e489c4f9d Re-enable 91381 with fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91489 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-16 00:53:11 +00:00
Evan Cheng
ad9c0a3d8b Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91381 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-15 00:53:42 +00:00
Evan Cheng
15b0d97068 Fix an obvious bug. No test case since LEA16r is not being used. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91219 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-12-12 18:51:56 +00:00
Dan Gohman
39a1fab856 Minor whitespace fixes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90166 91177308-0d34-0410-b5e6-96231b3b80d8
 2009-11-30 23:33:53 +00:00