Commit Graph

20761 Commits

Author SHA1 Message Date
Hal Finkel
a5d756ca39 Implement TTI getUnrollingPreferences for PowerPC
The PowerPC A2 core greatly benefits from aggressive concatenation unrolling;
use the new getUnrollingPreferences to enable this by default when targeting
the PPC A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190549 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 21:20:40 +00:00
Bill Wendling
8822f48f72 Try to fix the atom buildbots by adding an explicit 'cpu' to the 'llc' command.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190541 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 19:06:04 +00:00
Daniel Sanders
aa2a162eae [mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190522 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 12:39:25 +00:00
Daniel Sanders
f2eb1e4286 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190518 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 11:58:30 +00:00
Daniel Sanders
2ac1282921 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190512 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 10:51:30 +00:00
Daniel Sanders
ece929d623 [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190509 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 10:38:58 +00:00
Daniel Sanders
68831cbd41 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics)
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190507 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 10:28:16 +00:00
Daniel Sanders
8857294192 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics
The elements of the operands should be half the width of the elements of
the result.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190505 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 09:59:17 +00:00
Matt Arsenault
11250c1194 Teach loop-idiom about address space pointer sizes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190491 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-11 05:09:42 +00:00
Matt Arsenault
a03e32d397 Fix missing CHECK-LABELs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190426 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 19:57:05 +00:00
Matt Arsenault
14807bd8c8 Teach ScalarEvolution about pointer address spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190425 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 19:55:24 +00:00
Richard Sandiford
299fdd814f [SystemZ] Add TM and TMY
The main complication here is that TM and TMY (the memory forms) set
CC differently from the register forms.  When the tested bits contain
some 0s and some 1s, the register forms set CC to 1 or 2 based on the
value the uppermost bit.  The memory forms instead set CC to 1
regardless of the uppermost bit.

Until now, I've tried to make it so that a branch never tests for an
impossible CC value.  E.g. NR only sets CC to 0 or 1, so branches on the
result will only test for 0 or 1.  Originally I'd tried to do the same
thing for TM and TMY by using custom matching code in ISelDAGToDAG.
That ended up being very ugly though, and would have meant duplicating
some of the chain checks that the common isel code does.

I've therefore gone for the simpler alternative of adding an extra
operand to the TM DAG opcode to say whether a memory form would be OK.
This means that the inverse of a "TM;JE" is "TM;JNE" rather than the
more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE".
I suppose that's arguably less confusing though...


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190400 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 10:20:32 +00:00
Daniel Sanders
436f64567c [mips][msa] Removed unsupported dot product instructions (dotp_[su].b)
The dotp_[su].b instructions never existed in any revision of the MSA spec.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190398 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 09:51:43 +00:00
Vladimir Medic
b15da6dc09 Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of register when PFU is 32 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 09:50:01 +00:00
NAKAMURA Takumi
c3c9b9b7a8 MCObjectFileInfo.cpp: Fix a couple of possible typo(s), s/DwarfPub/DwarfGnuPub/, in r190344.
XFAIL can be removed. (in r190374)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190386 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 06:01:56 +00:00
NAKAMURA Takumi
db0e461511 llvm/test/DebugInfo/dwarf-public-names.ll: Mark it as XFAIL for PECOFF targets, for now. Investigating.
FIXME: llvm-dwarfdump doesn't handle PECOFF.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190374 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-10 00:28:23 +00:00
Manman Ren
d4fc36f264 Debug Info: In DIBuilder, the context fields of a TAG_inheritance and a
TAG_friend are updated to use scope reference.

Added testing cases to verify that class with inheritance can be uniqued.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 23:07:58 +00:00
Eli Friedman
b1c54930cb Don't shrink atomic ops to bool in GlobalOpt.
LLVM IR doesn't currently allow atomic bool load/store operations, and the
transformation is dubious anyway because it isn't profitable on all platforms.

PR17163.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190357 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 22:00:13 +00:00
Quentin Colombet
2c6ef1c433 [InstCombiner] Expose opportunities to merge subtract and comparison.
Several architectures use the same instruction to perform both a comparison and
a subtract. The instruction selection framework does not allow to consider
different basic blocks to expose such fusion opportunities.

Therefore, these instructions are “merged” by CSE at MI IR level.

To increase the likelihood of CSE to apply in such situation, we reorder the
operands of the comparison, when they have the same complexity, so that they
matches the order of the most frequent subtract.
E.g.,

icmp A, B
...
sub B, A

<rdar://problem/14514580>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190352 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:56:48 +00:00
Manman Ren
0b9ba182a7 Debug Info Testing: remove a commented out line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190351 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:45:34 +00:00
Bill Wendling
b0c8b25177 Another attempt to fix windows buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190350 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:29:32 +00:00
Bill Wendling
e1e9008e7c Attempt to fix buildbots by giving an explicit output to the llvm-mc command.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190349 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:22:38 +00:00
Bill Wendling
e93ad1a580 Expand test to make sure that we can generate compact unwind from an ASM file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190348 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:12:36 +00:00
Bill Wendling
4f02c41a36 Expand test to make sure that we can generate compact unwind from an ASM file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190347 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 20:10:54 +00:00
Manman Ren
2c9905a1f3 Debug Info: Use DIScopeRef for DIType::getContext.
In DIBuilder, the context field of a TAG_member is updated to use the
scope reference. Verifier is updated accordingly.
    
DebugInfoFinder now needs to generate a type identifier map to have
access to the actual scope. Same applies for BreakpointPrinter.
    
processModule of DebugInfoFinder is called during initialization phase
of the verifier to make sure the type identifier map is constructed early
enough.
    
We are now able to unique a simple class as demonstrated by the added
testing case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190334 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 19:47:11 +00:00
Bob Wilson
db3a9e64f8 Revert patches to add case-range support for PR1255.
The work on this project was left in an unfinished and inconsistent state.
Hopefully someone will eventually get a chance to implement this feature, but
in the meantime, it is better to put things back the way the were.  I have
left support in the bitcode reader to handle the case-range bitcode format,
so that we do not lose bitcode compatibility with the llvm 3.3 release.

This reverts the following commits: 155464, 156374, 156377, 156613, 156704,
156757, 156804 156808, 156985, 157046, 157112, 157183, 157315, 157384, 157575,
157576, 157586, 157612, 157810, 157814, 157815, 157880, 157881, 157882, 157884,
157887, 157901, 158979, 157987, 157989, 158986, 158997, 159076, 159101, 159100,
159200, 159201, 159207, 159527, 159532, 159540, 159583, 159618, 159658, 159659,
159660, 159661, 159703, 159704, 160076, 167356, 172025, 186736

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190328 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 19:14:35 +00:00
Joey Gouly
b57d99694b [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.
IT blocks can only be one instruction lonf, and can only contain a subset of
the 16 instructions.

Patch by Artyom Skrobov!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190309 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 14:21:49 +00:00
Robert Lytton
71537c1783 XCore handling of thread local lowering
Fix XCoreLowerThreadLocal trying to initialise globals
which have no initializer.

Add handling of const expressions containing thread local variables.
These need to be replaced with instructions, as the thread ID is
used to access the thread local variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190300 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 10:42:11 +00:00
Robert Lytton
7c739380ee XCore target: change to Sched::Source
This sidesteps a bug in PrescheduleNodesWithMultipleUses() which
does not check if callResources will be affected by the transformation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190299 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 10:42:05 +00:00
Robert Lytton
5c28673c3b XCore target: fix weak linkage attribute handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190298 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 10:41:57 +00:00
Bill Wendling
c3cee57f7d Generate compact unwind encoding from CFI directives.
We used to generate the compact unwind encoding from the machine
instructions. However, this had the problem that if the user used `-save-temps'
or compiled their hand-written `.s' file (with CFI directives), we wouldn't
generate the compact unwind encoding.

Move the algorithm that generates the compact unwind encoding into the
MCAsmBackend. This way we can generate the encoding whether the code is from a
`.ll' or `.s' file.

<rdar://problem/13623355>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 02:37:14 +00:00
Jiangning Liu
959cd8f49b Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the following 26 instructions,
SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 02:20:27 +00:00
Manman Ren
56736c18c1 Debug Info Testing: use null instead of an empty string in context field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190284 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-09 00:12:17 +00:00
Manman Ren
1ed2e1fb92 Debug Info Testing: update context from empty string to null.
Context should be either null or MDNode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190267 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-08 03:11:54 +00:00
Akira Hatanaka
0917ca56dc [mips] Fix typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190236 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 01:14:42 +00:00
Akira Hatanaka
3e6758541b [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:52:30 +00:00
Richard Smith
9401181aed Remove verifier check that attribute 'builtin' is only applied to calls to
functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190233 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:25:48 +00:00
Akira Hatanaka
1abf0afdd4 [mips] Add definition of instruction "drotr32" (double rotate right plus 32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:18:01 +00:00
Manman Ren
0e85f6e391 Debug Info: Use identifier to reference DIType in containing type field of
a DISubprogram.
    
Verifier is updated accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-07 00:04:05 +00:00
Akira Hatanaka
77e1ebd18f [mips] Set instruction itineraries of loads, stores and conditional moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 23:28:24 +00:00
Manman Ren
1307103dff Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields.
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190205 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 21:03:58 +00:00
Aaron Watry
546dcc5ddc R600: Add support for LDS atomic subtract
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 20:17:42 +00:00
Manman Ren
e42279cda4 Debug Info: Use identifier to reference DIType in containing type field of
a DICompositeType.
    
Verifier is updated accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190190 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 18:46:00 +00:00
Manman Ren
28da141d44 Debug Info Testing: Updated to use null instead of "i32 0" for containing-type
field of DICompositeType.

This will help the follow-on patch of using DITypeRef for containing-type field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190187 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 18:13:59 +00:00
Vladimir Medic
638382e6f1 This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 13:08:00 +00:00
Vladimir Medic
dadd1fba32 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:53:21 +00:00
Vladimir Medic
bf7f7b5e0e This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:41:17 +00:00
Tim Northover
a5eeb9da05 SelectionDAG: create correct BooleanContent constants
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190147 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:38:12 +00:00
Vladimir Medic
a674463aac This patch adds support for microMIPS disassembler and disassembler make check tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 12:30:36 +00:00
Richard Sandiford
aff1c6427c [SystemZ] Tweak integer comparison code
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-06 11:51:39 +00:00