25405 Commits

Author SHA1 Message Date
Suyog Sarda
1952b5a4da This patch implements transform for pattern "(A & ~B) ^ (~A) -> ~(A & B)".
Differential Revision: http://reviews.llvm.org/D4653



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214479 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 05:07:20 +00:00
Suyog Sarda
78061f4db4 This patch implements transform for pattern "(A | B) & ((~A) ^ B) -> (A & B)".
Differential Revision: http://reviews.llvm.org/D4628



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214478 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 04:59:26 +00:00
Suyog Sarda
d05b6c6f2c This patch implements transform for pattern "( A & (~B)) | (A ^ B) -> (A ^ B)"
Differential Revision: http://reviews.llvm.org/D4652



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214477 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 04:50:31 +00:00
Suyog Sarda
87569413b0 This patch implements transform for pattern "(A & B) | ((~A) ^ B) -> (~A ^ B)".
Patch Credit to Ankit Jain !

Differential Revision: http://reviews.llvm.org/D4655



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214476 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 04:41:43 +00:00
Juergen Ributzka
74ac16386b [FastISel][AArch64] Fix the immediate versions of the {s|u}{add|sub}.with.overflow intrinsics.
ADDS and SUBS cannot encode negative immediates or immediates larger than 12bit.
This fix checks if the immediate version can be used under this constraints and
if we can convert ADDS to SUBS or vice versa to support negative immediates.

Also update the test cases to test the immediate versions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214470 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 01:25:55 +00:00
Hal Finkel
bcaf5e176a [PowerPC] Recognize consecutive memory accesses from intrinsics
When generating unaligned vector loads, we need to search for other loads or
stores nearby offset by one vector width. If we find one, then we know that we
can safely generate another aligned load at that address. Otherwise, we must
generate the next load using an offset of the vector width minus one byte (so
we don't read off the end of the allocation if the base unaligned address
happened to be aligned at runtime). We had previously done this using only
other vector loads and stores, but did not consider the PowerPC-specific vector
load/store intrinsics. Now we'll also consider vector intrinsics. By itself,
this change is a feature enhancement, but is a necessary step toward fixing the
underlying problem behind PR19991.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214469 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 01:02:01 +00:00
Tom Stellard
17c8fefc9f R600/SI: Do abs/neg folding with ComplexPatterns
Abs/neg folding has moved out of foldOperands and into the instruction
selection phase using complex patterns.  As a consequence of this
change, we now prefer to select the 64-bit encoding for most
instructions and the modifier operands have been dropped from
integer VOP3 instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214467 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:39 +00:00
Tom Stellard
635fb9fb59 R600/SI: Fold immediates when shrinking instructions
This will prevent us from using extra MOV instructions once we prefer
selecting 64-bit instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214464 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:33 +00:00
Tom Stellard
e5fc4208eb R600/SI: Fix incorrect commute operation in shrink instructions pass
We were commuting the instruction by still shrinking it using the
original opcode.

NOTE: This is a candidate for the 3.5 branch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214463 91177308-0d34-0410-b5e6-96231b3b80d8
2014-08-01 00:32:28 +00:00
Kevin Enderby
42deb12738 Add support for the X86 secure guard extensions instructions in assembler (SGX).
This allows assembling the two new instructions, encls and enclu for the
SKX processor model.

Note the diffs are a bigger than what might think, but to fit the new
MRM_CF and MRM_D7 in things in the right places things had to be
renumbered and shuffled down causing a bit more diffs.

rdar://16228228


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214460 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:57:38 +00:00
Reid Kleckner
0b3444cca9 X86 MC: Don't crash on empty memory operand parens
Instead, create an absolute memory operand.

Fixes PR20504.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214457 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:26:35 +00:00
Reid Kleckner
7895ae3135 X86 MC: Reject invalid segment registers before a memory operand colon
Previously we would execute unreachable during object emission.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214456 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 23:03:22 +00:00
Jan Vesely
22c99ee827 R600: Modernize work item intrinsics test
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Matt Arsenault <Matthew.Arsenault@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214451 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 22:11:03 +00:00
Tyler Nowicki
f7be7f15c1 Improve the remark generated for -Rpass-missed.
The current remark is ambiguous and makes it sounds like explicitly specifying vectorization will allow the loop to be vectorized. This is not the case. The improved remark directs the user to -Rpass-analysis=loop-vectorize to determine the cause of the pass-miss.

Reviewed by Arnold Schwaighofer`


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:22:22 +00:00
Tyler Nowicki
88212074a8 Improve the remark generated when a variable that is used outside the loop is not a reduction or induction variable.
Reviewed by Arnold Schwaighofer


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214440 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 21:02:40 +00:00
Will Schmidt
723bdb5e3f Disable IsSub subregister assert. pr18663.
This is a follow-up to the activity in the bug at
http://llvm.org/bugs/show_bug.cgi?id=18663 .  The underlying issue has
to do with how the KILL pseudo-instruction is handled.  I defer to
Hal/Jakob/Uli for additional details and background.

This will disable the (bad?) assert, add an associated fixme comment,
and add a pair of tests.

The code change and the pr18663-2.ll test are copied from the referenced
bug.  That test does not immediately fail in my environment, but I have
added the pr18663.ll test which does.

(Comment from Hal)
to provide everyone else with some context, this assert was not bad when
it was written. At that time, we only generated KILL pseudo instructions
around subregister copies. This logic, unfortunately, had its own problems.
In r199797, the relevant logic in MachineCopyPropagation was replaced to
generate KILLs for other kinds of copies too. This change in semantics broke
this now-problematic assumption in AggressiveAntiDepBreaker. The
AggressiveAntiDepBreaker really needs a proper cleanup to deal with the
change, but removing the assert (which just allows the function to return
false) is a safe conservative behavior, and should do for the time being.






git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214429 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 19:50:53 +00:00
Hal Finkel
50c05c91f9 Fix ScalarEvolutionExpander when creating a PHI in a block with duplicate predecessors
It seems that when I fixed this, almost exactly a year ago, I did not quite do
it correctly. When we have duplicate block predecessors, we can indeed not have
different incoming values for the same block, but we *must* have duplicate
entries. So, instead of skipping the duplicates, we explicitly add the
duplicate incoming values.

Fixes PR20442.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214423 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 19:13:38 +00:00
Duncan P. N. Exon Smith
94f7c7aeaa verify-uselistorder: Change the default -num-shuffles=5
Change the default for `-num-shuffles` to 5 and better document the
algorithm in the header docs of `verify-uselistorder`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 18:46:24 +00:00
Duncan P. N. Exon Smith
9d65d3717c UseListOrder: Handle self-users
Correctly sort self-users (such as PHI nodes).  I added a targeted test
in `test/Bitcode/use-list-order.ll` and the final missing RUN line to
tests in `test/Assembly`.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214417 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 18:33:12 +00:00
Evgeniy Stepanov
7ee4f09c94 [msan] Fix handling of array types.
Switch array type shadow from a single integer to
an array of integers (i.e. make it per-element).
This simplifies instrumentation of extractvalue and fixes PR20493.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214398 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 11:02:27 +00:00
Evgeniy Stepanov
8a78bb9836 [asan] Support x86 REP MOVS asm instrumentation.
Patch by Yuri Gorshenin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214395 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 09:11:04 +00:00
Juergen Ributzka
95ec2761f3 [FastISel][AArch64] Add basic bitcast support for conversion between float and int.
Fixes <rdar://problem/17867078>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214389 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 06:25:37 +00:00
Juergen Ributzka
a60ed423a6 [FastISel][AArch64] Add sqrt intrinsic support.
Fixes <rdar://problem/17867067>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214388 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 06:25:33 +00:00
David Majnemer
a4a812fedd InstCombine: Correctly propagate NSW/NUW for x-(-A) -> x+A
We can only propagate the nsw bits if both subtraction instructions are
marked with the appropriate bit.

N.B.  We only propagate the nsw bit in InstCombine because the nuw case
is already handled in InstSimplify.

This fixes PR20189.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214385 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 04:49:29 +00:00
David Majnemer
ec7ee07036 InstSimplify: Simplify (X - (0 - Y)) if the second sub is NUW
If the NUW bit is set for 0 - Y, we know that all values for Y other
than 0 would produce a poison value.  This allows us to replace (0 - Y)
with 0 in the expression (X - (0 - Y)) which will ultimately leave us
with X.

This partially fixes PR20189.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214384 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 04:49:18 +00:00
Juergen Ributzka
e482ebc147 [FastISel][AArch64] Update and enable patchpoint and stackmap intrinsic tests for FastISel.
This commit updates the existing SelectionDAG tests for the stackmap and patchpoint
intrinsics and enables FastISel testing. It also splits up the tests into separate
files, due to different codegen between SelectionDAG and FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214382 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 04:10:43 +00:00
Juergen Ributzka
e3a75015d7 [FastISel][AArch64] Add MachO large code model support for function calls.
Currently the large code model for MachO uses the GOT to make function calls.
Emit the required adrp and ldr instructions to load the address from the GOT.

Related to <rdar://problem/17733076>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214381 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 04:10:40 +00:00
Duncan P. N. Exon Smith
e5ae09b08f UseListOrder: Don't give constant IDs to GlobalValues
Since initializers of GlobalValues are being assigned IDs before
GlobalValues themselves, explicitly exclude GlobalValues from the
constant pool.  Added targeted test in `test/Bitcode/use-list-order.ll`
and added two more RUN lines in `test/Assembly`.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214368 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 00:13:28 +00:00
Juergen Ributzka
dc6c25c9ee [FastISel] Fix the patchpoint intrinsic lowering in FastISel for large target addresses.
This fixes a mistake where I accidentially dropped the upper 32bit of a
64bit pointer during FastISel lowering of the patchpoint intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214367 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 00:11:16 +00:00
Juergen Ributzka
450c33b212 [FastISel][AArch64 and X86] Don't emit stores for UNDEF arguments during function call lowering.
UNDEF arguments are not ment to be touched - especially for the webkit_js
calling convention. This fix reproduces the already existing behavior of
SelectionDAG in FastISel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214366 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 00:11:11 +00:00
Duncan P. N. Exon Smith
d321cdfc1c verify-uselistorder: Add RUN lines to cases in test/Assembly
Add RUN line for `verify-uselistorder` to every test in `test/Assembly`,
unless it's a negative check (assembler rejects it) or verification
fails.

There are three files that verification fails on (so I've left out the
RUN lines):

  - 2002-08-22-DominanceProblem.ll
  - ConstantExprFold.ll
  - ConstantExprFoldCast.ll

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214365 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-31 00:10:27 +00:00
Joerg Sonnenberger
cadb2a8a32 Add mtpid/mfpid for BookE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214363 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 23:59:11 +00:00
Justin Bogner
c222d610dd llvm-profdata: Add a test for mismatched numbers of counters
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214360 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 23:36:06 +00:00
Justin Bogner
2adcddcd84 llvm-profdata: Use consistent file suffixes in tests
In some places we've been using different suffixes for the different
file formats involved in instrprof, but in others we've just
ambiguously used .profdata. Update the test files to indicate the
types of file more obviously.

No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214357 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 23:02:01 +00:00
Rafael Espindola
d57120551f Use "weak alias" instead of "alias weak"
Before this patch we had

@a = weak global ...
but
@b = alias weak ...

The patch changes aliases to look more like global variables.

Looking at some really old code suggests that the reason was that the old
bison based parser had a reduction for alias linkages and another one for
global variable linkages. Putting the alias first avoided the reduce/reduce
conflict.

The days of the old .ll parser are long gone. The new one parses just "linkage"
and a later check is responsible for deciding if a linkage is valid in a
given context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214355 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 22:51:54 +00:00
Joerg Sonnenberger
367c5c25e8 Refactor TLBIVAX and add tlbsx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214354 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 22:51:15 +00:00
Juergen Ributzka
cb99212bc1 [FastISel][AArch64] Add select folding support for the XALU intrinsics.
This improves the code generation for the XALU intrinsics when the
condition is feeding a select instruction.

This also updates and enables the XALU unit tests for FastISel.

This fixes <rdar://problem/17831117>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 22:04:37 +00:00
Juergen Ributzka
b0dba10fa6 [FastISel][AArch64] Add support for shift-immediate.
Currently the shift-immediate versions are not supported by tblgen and
hopefully this can be later removed, once the required support has been
added to tblgen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214345 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 22:04:22 +00:00
David Majnemer
5624046453 InstCombine: Simplify (A ^ B) or/and (A ^ B ^ C)
While we can already transform A | (A ^ B) into A | B, things get bad
once we have (A ^ B) | (A ^ B ^ Cst) because reassociation will morph
this into (A ^ B) | ((A ^ Cst) ^ B).  Our existing patterns fail once
this happens.

To fix this, we add a new pattern which looks through the tree of xor
binary operators to see that, in fact, there exists a redundant xor
operation.

What follows bellow is a correctness proof of the transform using CVC3.

$ cat t.cvc
A, B, C : BITVECTOR(64);

QUERY BVXOR(A, B) | BVXOR(BVXOR(B, C), A) = BVXOR(A, B) | C;
QUERY BVXOR(BVXOR(A, C), B) | BVXOR(A, B) = BVXOR(A, B) | C;

QUERY BVXOR(A, B) & BVXOR(BVXOR(B, C), A) = BVXOR(A, B) & ~C;
QUERY BVXOR(BVXOR(A, C), B) & BVXOR(A, B) = BVXOR(A, B) & ~C;

$ cvc3 < t.cvc
Valid.
Valid.
Valid.
Valid.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214342 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 21:26:37 +00:00
Joerg Sonnenberger
ee6a05091a Add rfdi and rfmci from the e500/e500mc ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214339 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 21:09:03 +00:00
Chad Rosier
7f6a685444 SLP Vectorizer: Canonicalize tree operands of commutitive binary operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214338 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 21:07:56 +00:00
Rafael Espindola
7fef5a3d19 SimplifyCFG: Avoid miscompilations due to removed lifetime intrinsics.
The lifetime intrinsics need some work in order to make it clear which
optimizations are or are not valid.

For now dropping this optimization avoids a miscompilation.

Patch by Björn Steinbrink.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214336 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 21:04:00 +00:00
Joerg Sonnenberger
9e3d58aae1 Add BookE's tlbre, tlbwe and tlbivax instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214332 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 20:44:04 +00:00
Louis Gerbarg
8f345158a1 Fix test case introduced in r214322
This patch adds an explicit triple to the test case introduced by r214322. This
should fix build failueres that are occuring on bots that are cross building.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214330 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 20:26:09 +00:00
Louis Gerbarg
5fb3c84898 Retain alignment requirements for load->selects modified by DAGCombine
DAGCombine may choose to rewrite graphs where two loads feed a select into
graphs where a select of two addresses feed a load. While it sanity checks the
loads to make sure they are broadly equivalent it currently just uses the
alignment restriction of the left node. In cases where the right node has
stronger alignment requiresment this may lead to bad codegen, such as generating
an aligned load where an unaligned load is required. This patch makes the
combine generate a load with an alignment that is the same as whichever is more
restrictive of the two alignments.

Tests included.

rdar://17762530

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214322 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 18:24:41 +00:00
Duncan P. N. Exon Smith
43b54db2a4 UseListOrder: Visit global values
When predicting use-list order, we visit functions in reverse order
followed by `GlobalValue`s and write out use-lists at the first
opportunity.  In the reader, this will translate to *after* the last use
has been added.

For this to work, we actually need to descend into `GlobalValue`s.
Added a targeted test in `use-list-order.ll` and `RUN` lines to the
newly passing tests in `test/Bitcode`.

There are two remaining failures in `test/Bitcode`:

  - blockaddress.ll: I haven't thought through how to model the way
    block addresses change the order of use-lists (or how to work around
    it).

  - metadata-2.ll: There's an old-style `@llvm.used` global array here
    that I suspect the .ll parser isn't upgrading properly.  When it
    round-trips through bitcode, the .bc reader *does* upgrade it, so
    the extra variable (`i8* null`) has an extra use, and the shuffle
    vector doesn't match.

    I think the fix is to upgrade old-style global arrays (or reject
    them?) in the .ll parser.

This is part of PR5680.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214321 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 17:51:09 +00:00
Duncan P. N. Exon Smith
8dc3e30075 Fix line endings before adding RUN lines, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214320 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 17:49:00 +00:00
Duncan P. N. Exon Smith
89c4197256 Rename llvm-uselistorder => verify-uselistorder
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214318 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 17:11:27 +00:00
Rafael Espindola
d59fa04f04 Add a small test showing when a linkonce_odr symbol can be hidden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214311 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 15:31:21 +00:00
Joerg Sonnenberger
a4d6ef15b8 Add BookE's wrtee and wrteei instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214297 91177308-0d34-0410-b5e6-96231b3b80d8
2014-07-30 10:32:51 +00:00