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246 Commits

Author SHA1 Message Date
Jyotsna Verma
1a7eab3878 Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:49:23 +00:00
Krzysztof Parzyszek
ed6fe299cf Make references to HexagonTargetMachine "const". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181233 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-06 18:38:37 +00:00
Krzysztof Parzyszek
cc420a0911 Use consistent function names. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181090 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-04 01:30:49 +00:00
Reid Kleckner
aa35a56975 Fix missing include in Hexagon code for Release+Asserts 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180983 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-03 00:54:56 +00:00
Jyotsna Verma
d4f8a6b9e9 reverting r180953 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 22:10:59 +00:00
Jyotsna Verma
8a3f50038f Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 21:21:57 +00:00
Pranav Bhandarkar
02d937d864 Hexagon - Add peephole optimizations for zero extends. 
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a
	sequence of a pair of i32->i64 extensions followed by a "bitwise or"
	into COMBINE_rr.
	* lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the
	instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg.
	* test/CodeGen/Hexagon/union-1.ll: New test.
	* test/CodeGen/Hexagon/combine_ir.ll: Fix test.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 20:22:51 +00:00
Jyotsna Verma
f945d09d53 Hexagon: Honor __builtin_expect by using branch probabilities. 
* lib/Target/Hexagon/HexagonInstrInfo.cpp (GetDotNewPredOp):
  Given a jump opcode return the right pred.new jump opcode with
  a taken vs not-taken hint based on branch probabilities provided
  by the target independent module.
  * lib/Target/Hexagon/HexagonVLIWPacketizer.cpp: Use the above function.
  * lib/Target/Hexagon/HexagonNewValueJump.cpp(getNewvalueJumpOpcode):
  Enhance existing function use branch probabilities like
  HexagonInstrInfo::GetDotNewPredOp but for New Value (GPR) Jumps.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180923 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-02 15:39:30 +00:00
Jyotsna Verma
6ea706e40e Hexagon: Use multiclass for Jump instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 21:37:34 +00:00
Jyotsna Verma
f9759c9f08 Hexagon: Clear isKill flag on the predicate register in 
PredicateInstruction function.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180884 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-05-01 21:27:30 +00:00
Jyotsna Verma
42ba77db53 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:17:40 +00:00
Jyotsna Verma
197c833ee1 Hexagon: Define relations for GP-relative instructions. 
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 21:05:55 +00:00
Jyotsna Verma
47089c91ae Hexagon: Remove assembler mapped instruction definitions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 19:15:55 +00:00
Jyotsna Verma
3d7b39e7d4 Hexagon: Remove duplicate instructions to handle global/immediate values 
for absolute/absolute-set addressing modes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-23 17:11:46 +00:00
Tim Northover
6265d5c91a Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179939 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-20 12:32:17 +00:00
Michael Liao
2a8bea7a8e ArrayRefize getMachineNode(). No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-19 22:22:57 +00:00
Jyotsna Verma
1877dc00e7 Hexagon: Set isPredicatedNew flag on predicate new instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 18:01:06 +00:00
Jyotsna Verma
c1406d76ec Hexagon: Set isPredicatedFlase flag for all the instructions with negated predication. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-12 17:46:52 +00:00
Jyotsna Verma
0e58d92628 Hexagon: Expand br_cc. 
It fixes following tests for Hexagon:

CodeGen/Generic/2003-07-29-BadConstSbyte.ll
CodeGen/Generic/2005-10-21-longlonggtu.ll
CodeGen/Generic/2009-04-28-i128-cmp-crash.ll
CodeGen/Generic/MachineBranchProb.ll
CodeGen/Generic/builtin-expect.ll
CodeGen/Generic/pr12507.ll



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178794 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-04 21:18:26 +00:00
Duncan Sands
0857a6fd33 Remove unused typedef. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178462 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-04-01 13:46:15 +00:00
Duncan Sands
79f615cbfe There is no longer any need to silence this compiler warning as the warning has 
been turned off globally.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178451 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-31 17:44:09 +00:00
Jyotsna Verma
2a88555e0d Hexagon: Add emitFrameIndexDebugValue function to emit debug information. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178368 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-29 21:09:53 +00:00
Jyotsna Verma
65063feac5 Hexagon: Disable DwarfUsesInlineInfoSection flag. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178345 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-29 15:46:12 +00:00
Jyotsna Verma
810848d5b3 Hexagon: Replace switch-case in isDotNewInst with TSFlags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178281 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 19:44:04 +00:00
Jyotsna Verma
e41c7d4890 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 19:34:49 +00:00
Jyotsna Verma
4f2ef94d6a Hexagon: Use multiclass for gp-relative instructions. 
Remove noV4T gp-relative instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-28 16:25:57 +00:00
Tim Northover
fe37e6279e Switch to LLVM support function abs64 to keep VS2008 happy. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178141 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-27 13:15:08 +00:00
Jyotsna Verma
0f680703eb Hexagon: Disable optimizations at O0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178132 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-27 11:14:24 +00:00
Jyotsna Verma
7bb9585c6e Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:43:57 +00:00
Jyotsna Verma
a8c8c45838 Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/HexagonMCInst.h. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178030 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-26 15:34:22 +00:00
Jyotsna Verma
97e602b574 Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-22 18:41:34 +00:00
Jyotsna Verma
cec50e6da2 Hexagon: Removed asserts regarding alignment and offset. 
We are warning the user about the alignment, so we should not assert.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-14 19:08:03 +00:00
Jakub Staszak
760fa5dc80 Cleanup #includes. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176787 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-10 13:11:23 +00:00
Tom Stellard
3ef5383b35 DAGCombiner: Use correct value type for checking legality of BR_CC v3 
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 15:36:57 +00:00
Jyotsna Verma
86df21767a Hexagon: Add patterns for zero extended loads from i1->i64. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-08 14:15:15 +00:00
Jyotsna Verma
a4dd8d6732 Hexagon: Handle i8, i16 and i1 Var Args. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 20:28:34 +00:00
Jyotsna Verma
b6716187ca Hexagon: Add support to lower block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-07 19:10:28 +00:00
Jyotsna Verma
0d44328ce8 reverting patch 176508. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 20:29:23 +00:00
Jyotsna Verma
c34f17140f Hexagon: Add support for lowering block address. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:37:46 +00:00
Jyotsna Verma
18daead3ff Hexagon: Expand addc, adde, subc and sube. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 19:04:47 +00:00
Jyotsna Verma
9feabc23b3 Hexagon: Use MO operand flags to mark constant extended instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176500 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:51:42 +00:00
Jyotsna Verma
ee0ef13eba Hexagon: Add encoding bits to the TFR64 instructions. 
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-05 18:42:28 +00:00
Andrew Trick
1c01af8f26 Added FIXME for future Hexagon cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176400 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-02 01:43:08 +00:00
Jyotsna Verma
ef94c6c85e Hexagon: Add constant extender support framework. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-03-01 17:37:13 +00:00
Andrew Trick
667754e239 Remove code copied from GenRegisterInfo.inc. 
There's no apparent reason this code was copied from generated source
into a .cpp. It sets a bad example for those working on other targets
and trying to understand the register info API.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-22 01:15:08 +00:00
Eli Bendersky
700ed80d3d Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-21 20:05:00 +00:00
Anshuman Dasgupta
6585d3b64b Hexagon: Expand cttz, ctlz, and ctpop for now. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-21 19:39:40 +00:00
Jim Grosbach
3450f800aa Update TargetLowering ivars for name policy. 
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 21:13:59 +00:00
Jyotsna Verma
d6c98ae638 Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. 
Add HexagonMCInst class which adds various Hexagon VLIW annotations.
In addition, this class also includes some APIs related to the
constant extenders.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175634 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-20 16:13:27 +00:00
Jyotsna Verma
383c6fc458 Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with 
HexagonInstrFormats.td.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175537 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-02-19 18:18:36 +00:00