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16569 Commits

Author SHA1 Message Date
Chris Lattner
14b93851cc add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-29 00:27:31 +00:00
Chris Lattner
e73d4f8ec7 give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 21:41:58 +00:00
Chris Lattner
6274ec48b3 hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes 
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 21:37:33 +00:00
Chris Lattner
fa42fad8bf move a method out of line. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117605 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 21:28:01 +00:00
Chris Lattner
550276ee5b remove the rest of hte owningptr's, no functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117603 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 20:52:15 +00:00
Benjamin Kramer
57ca3ccd45 Reduce malloc thrashing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117572 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 18:41:23 +00:00
Jim Grosbach
ab682a2090 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 18:34:10 +00:00
Chris Lattner
c0ddfaa134 rearrange ParseRegisterList. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 17:23:41 +00:00
Chris Lattner
3a69756e39 refactor some code to simplify it, eliminating some owningptr's. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117559 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 17:20:03 +00:00
Evan Cheng
7e2fe9150f Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117531 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 06:47:08 +00:00
Evan Cheng
9e08ee5d16 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117520 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 02:00:25 +00:00
Evan Cheng
0104d9de04 - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117519 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 01:49:06 +00:00
Dale Johannesen
e49406fd63 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117514 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 00:35:54 +00:00
Owen Anderson
cfd0e1f3ae Add correct NEON encodings for vtbl and vtbx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-28 00:18:46 +00:00
Owen Anderson
3eff4af42d Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:56:39 +00:00
Bob Wilson
1fa9d301a8 Fix compiler warnings about signed/unsigned comparisons. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:49:00 +00:00
Evan Cheng
f40deed62f Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117509 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:41:30 +00:00
Jim Grosbach
7e3383c007 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117505 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 23:12:14 +00:00
Owen Anderson
498ec20703 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 22:49:00 +00:00
Jim Grosbach
6b15639e26 Trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117496 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 21:39:08 +00:00
Owen Anderson
d2fbdb7f5c Provide correct encodings for the get_lane and set_lane variants of vmov. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 21:28:09 +00:00
Kevin Enderby
529b1a4398 Added the x86 instruction ud2b (2nd official undefined instruction). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:46:49 +00:00
Jim Grosbach
ccf72caa92 JIT imm12 encoding for constant pool entry references. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117483 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:39:40 +00:00
Bob Wilson
f20700ca77 SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 20:38:28 +00:00
Jim Grosbach
f31430f6ec ARM JIT fix for LDRi12 and company. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117478 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 19:55:59 +00:00
Owen Anderson
f587a9352a Provide correct NEON encodings for vdup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 19:25:54 +00:00
Michael J. Spencer
6dad10ed66 x86-Win32: Switch ftol2 calling convention from stdcall to C. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117474 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 18:52:38 +00:00
Jim Grosbach
093177d5cd The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117461 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:52:51 +00:00
Owen Anderson
0745c389d9 Add correct NEON encodings for vsli and vsri. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:40:08 +00:00
Owen Anderson
dd31ed67e6 Add correct NEON encodings for vsra and vrsra. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 17:29:29 +00:00
Jim Grosbach
063efbf569 The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117454 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 16:50:31 +00:00
Kevin Enderby
e460890351 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 03:01:02 +00:00
Kevin Enderby
5a378076a4 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 02:53:04 +00:00
Kevin Enderby
f4630ecc3f Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 02:32:19 +00:00
Jim Grosbach
77aee8e22c LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 01:19:41 +00:00
Kevin Enderby
41e8cc73cf Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:59:28 +00:00
Jim Grosbach
f85dd04bfa One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117421 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:38:16 +00:00
Wesley Peck
a06038369b Adding disassembler to the MicroBlaze backend. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117420 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:23:01 +00:00
Jim Grosbach
c1d30212e9 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117419 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-27 00:19:44 +00:00
Jim Grosbach
28e3fe961f Since I parameterized this bit, I should probably actually use said parameter. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117418 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 23:58:04 +00:00
Dale Johannesen
1de4aa904e Use a MemIntrinsicSDNode for ISD::PREFETCH, which touches 
memory, so a MachineMemOperand is useful (not propagated
into the MachineInstr yet).  No functional change except
for dump output.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117413 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 23:11:10 +00:00
Owen Anderson
86ed2324a6 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 22:50:46 +00:00
Jim Grosbach
3e55612472 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 22:37:02 +00:00
Owen Anderson
632c235a31 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 21:58:41 +00:00
Owen Anderson
ac92262b61 Simplify classes for shift instructions, which are never commutable. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117398 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 21:13:59 +00:00
Owen Anderson
3557d00a38 Provide correct NEON encodings for vshl, register and immediate forms. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 20:56:57 +00:00
Jim Grosbach
0eb7d06ab1 Grammar. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117388 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 19:34:41 +00:00
Jim Grosbach
c3baf62800 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117387 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 19:22:23 +00:00
Owen Anderson
bc4118bd36 Add correct NEON encoding for vpadal. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 18:18:03 +00:00
Rafael Espindola
de42e5c09b handle X86::EH_RETURN64 and X86::EH_RETURN. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117378 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-10-26 18:09:55 +00:00