 Silviu Baranga
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169e9ba2b2
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Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-05-11 09:28:27 +00:00 |
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Silviu Baranga
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ca3cd419a5
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Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-05-11 09:10:54 +00:00 |
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Silviu Baranga
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b422d0b65e
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Fixed disassembler for vstm/vldm ARM VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-05-03 16:38:40 +00:00 |
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Silviu Baranga
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35ee7d28a6
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Added support for disassembling unpredictable swp/swpb ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-18 14:18:57 +00:00 |
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Silviu Baranga
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6b9f97dd89
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Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-18 14:09:07 +00:00 |
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Silviu Baranga
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fa1ebc6abe
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Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-18 13:12:50 +00:00 |
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Silviu Baranga
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e546c4c9c3
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Fixed decoding for the ARM cdp2 instruction. The restriction on the coprocessor number was removed for this instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-18 13:02:55 +00:00 |
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Silviu Baranga
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9e71231309
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Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM instructions in the disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-18 12:48:43 +00:00 |
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Silviu Baranga
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1c01249191
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Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-05 16:19:29 +00:00 |
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Silviu Baranga
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82e1bba0e4
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Added support for handling unpredictable arithmetic instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-05 16:13:15 +00:00 |
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Silviu Baranga
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545b962f15
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Second part for the 153874 one
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153875 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-02 15:46:46 +00:00 |
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Silviu Baranga
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50ac2e9229
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Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153874 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-04-02 15:20:39 +00:00 |
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Silviu Baranga
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6fe310e155
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Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153252 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-03-22 14:14:49 +00:00 |
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Silviu Baranga
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b7c2ed6664
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Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153251 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-03-22 13:24:43 +00:00 |
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Silviu Baranga
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a0c48eb8f6
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Added soft fail cases for the disassembler when decoding MUL instructions on ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153250 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-03-22 13:14:39 +00:00 |
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Silviu Baranga
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5c062ad926
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The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153089 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-03-20 15:54:56 +00:00 |
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Silviu Baranga
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8da7a4668f
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test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153086 91177308-0d34-0410-b5e6-96231b3b80d8
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2012-03-20 13:12:38 +00:00 |
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