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3102 Commits

Author SHA1 Message Date
Jim Grosbach
1dc335a79f Simplify ARM callee-saved register handling by removing the distinction 
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-20 19:32:20 +00:00
Michael J. Spencer
895dda6fb5 Fix build. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 17:54:37 +00:00
Eric Christopher
c109556a0a Thumb opcodes for thumb calls. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 02:32:38 +00:00
Eric Christopher
6dab137b88 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 01:59:37 +00:00
Eric Christopher
b74558ad3e Floating point stores have a 3rd addressing mode type. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 01:23:38 +00:00
Jim Grosbach
988ce097b7 factor out a simple helper function to create a label for PC-relative 
instructions (PICADD, PICLDR, et.al.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 00:05:05 +00:00
Jim Grosbach
d30cfde935 PC-relative pseudo instructions are lowered and printed directly. Any encounter 
with one in the generic printing code is an error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-18 00:04:53 +00:00
Benjamin Kramer
92aa1f7123 Fix vmov.f64 disassembly on targets where sizeof(long) != 8. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 23:48:07 +00:00
Jim Grosbach
fbd1873041 Add MC-inst handling for tPICADD 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 23:41:53 +00:00
Bob Wilson
75f0288b7d Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:59:05 +00:00
Jim Grosbach
e6be85e9ff Teach the (non-MC) instruction printer to use the cannonical names for push/pop, 
and shift instructions on ARM. Update the tests to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:36:38 +00:00
Eric Christopher
a5b1e68107 Rework arm fast isel branch and compare code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 22:28:18 +00:00
Jim Grosbach
74d7e6c64e Hook up verbose asm comment printing for SOImm operands in MC printer 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 21:33:25 +00:00
Jim Grosbach
196b48b708 trailing whitespace 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 21:25:10 +00:00
Jim Grosbach
568eeedea7 Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 18:46:17 +00:00
Jim Grosbach
c686e33d12 handle the upper16/lower16 target operand flags on symbol references for MC 
instruction lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 18:25:25 +00:00
Jim Grosbach
a28abbe245 expand PICLDR MC lowering to handle other PICLDR and PICSTR versions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-17 16:25:52 +00:00
Jim Grosbach
b74ca9d631 MC-ization of the PICLDR pseudo. Next up, adding the other variants 
(PICLDRB, et. al.) and PICSTR*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 17:43:25 +00:00
Jim Grosbach
1d51c41a45 Make sure to promote single precision floats to double before extracting them 
from the APFloat.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 17:37:30 +00:00
Bob Wilson
de0ae8f83d Remove support for "dregpair" operand modifier, now that it is no longer being 
used for anything.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 04:55:00 +00:00
Bob Wilson
823611bfba When expanding ARM pseudo registers, copy the existing predicate operands 
instead of using default predicates on the expanded instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 04:25:37 +00:00
Jim Grosbach
a8e47b3319 store MC FP immediates as a double instead of as an APFloat, thus avoiding an 
unnecessary dtor for MCOperand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 03:45:21 +00:00
Bob Wilson
ea606bb76b Add missing break. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 00:31:32 +00:00
Bob Wilson
9d4ebc0eb8 Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after 
register allocation to VLDMD and VSTMD respectively.  This avoids using the
dregpair operand modifier.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-16 00:31:02 +00:00
Jim Grosbach
765c4d9477 Add support for the 'lane' modifier on vdup operands 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 22:13:23 +00:00
Jakob Stoklund Olesen
06f264e504 Remember VLDMQ. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 21:40:11 +00:00
Jakob Stoklund Olesen
31bbc51ac9 Add missing break. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114025 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 21:40:09 +00:00
Jim Grosbach
60396975be Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register 
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114021 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 21:04:54 +00:00
Jim Grosbach
a4c3c8f28d move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helper 
functions in ARMBaseInfo.h so it can be used in the MC library as well.
For anything bigger than this, we may want a means to have a small support
library for shared helper functions like this. Cross that bridge when we
come to it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114016 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 20:26:25 +00:00
Jim Grosbach
f1c3eb37ae simplify getRegisterNumbering(). Remove the unused isSPVFP argument and 
merge the common cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114013 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 19:52:17 +00:00
Jim Grosbach
7e2c04fd05 Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. Check 
if the register is a member of the SPR register class directly instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114012 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 19:44:57 +00:00
Jim Grosbach
d8be410d4b Reduce dependencies in the ARM MC instruction printer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114009 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 19:27:50 +00:00
Jim Grosbach
8b7fa198c3 Fix spelling typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114008 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 19:26:50 +00:00
Jim Grosbach
754578b565 Factor out basic enums and hleper functions from ARM.h for cleaner sharing 
between the compiler back end and the MC libraries.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114007 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 19:26:06 +00:00
Jim Grosbach
26edbcb8d5 Add support for floating point immediates to MC instruction printing. ARM 
VFP instructions use it for loading some constants, so implement that
handling.

Not thrilled with adding a member to MCOperand, but not sure there's much of
a better option that's not pretty fragile (like putting a double in the
union instead and just assuming that's good enough). Suggestions welcome...



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 18:47:08 +00:00
Jakob Stoklund Olesen
d64816a8d0 Recognize VST1q64Pseudo and VSTMQ as stack slot stores. 
Recognize VLD1q64Pseudo as a stack slot load.

Reject these if they are loading or storing a subregister. The API (and
VirtRegRewriter) doesn't know how to deal with that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113985 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 17:27:09 +00:00
Bob Wilson
3a951829fe Reapply Gabor's 113839, 113840, and 113876 with a fix for a problem 
encountered while building llvm-gcc for arm.  This is probably the same issue
that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator,
not a plain MachineInstr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113983 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 17:12:08 +00:00
Gabor Greif
7602993f2d the darwin9-powerpc buildbot keeps consistently crashing, 
backing out following to get it back to green,
so I can investigate in peace:

svn merge -c -113840  llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll
svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113980 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 16:53:07 +00:00
Jakob Stoklund Olesen
34327856d9 Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't be 
forgotten in the future.

Coalesce identical cases in switch.

No functional changes intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113979 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 16:36:26 +00:00
Bob Wilson
064312de86 Spelling fix. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113978 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 16:28:21 +00:00
Bob Wilson
168f382dc6 Use VLD1/VST1 pseudo instructions for loadRegFromStackSlot and 
storeRegToStackSlot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113918 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-15 01:48:05 +00:00
Jim Grosbach
05ae0c6026 Reapply r113875 with additional cleanups. 
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."

Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113903 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 23:54:06 +00:00
Eric Christopher
bb3e5dad66 Emit libcalls for SDIV, this requires some call infrastructure 
that needs to be shared a bit more widely around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113886 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 23:03:37 +00:00
Jim Grosbach
684193928c revert 113875 momentarilly. Need to fix the MC disassembler to handle the 
change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113878 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 22:38:39 +00:00
Jim Grosbach
15d78984d5 trailing whitespace cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113877 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 22:27:15 +00:00
Gabor Greif
308f64a7c8 an attempt to salvage the darwin9-powerpc buildbot, which could be miscompiling this line 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113876 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 22:25:16 +00:00
Jim Grosbach
fe125557dd The register specified for a dregpair is the corresponding Q register, so to 
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01]).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113875 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 22:20:33 +00:00
Gabor Greif
f7d10f5c12 set isCompare for another three Thumb1 instructions 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113867 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 22:00:50 +00:00
Jim Grosbach
5b46d62c44 Add predicate and 's' bit operands to PICADD instruction lowering. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113860 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 21:28:17 +00:00
Bob Wilson
fe3ac088ee Avoid warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113857 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-09-14 21:12:05 +00:00