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15461 Commits

Author SHA1 Message Date
Nate Begeman
0e0a20eb38 Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109813 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 22:48:09 +00:00
Bob Wilson
3d5792a5aa Refactor ARM-specific DAG combining in preparation for adding some more
transformations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109800 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 20:34:14 +00:00
Dale Johannesen
f630c712b1 Implement vector constants which are splat of
integers with mov + vdup.  8003375.  This is
currently disabled by default because LICM will
not hoist a VDUP, so it pessimizes the code if
the construct occurs inside a loop (8248029).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109799 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 20:10:08 +00:00
Bob Wilson
fb13b95162 Don't assert on an unrecognized BrMiscFrm instruction.
PR7745.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109788 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 18:29:28 +00:00
Nate Begeman
692433bc2d Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the QADD & QSUB instructions.
Behave identically to __qadd & __qsub RealView instruction intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109770 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 17:56:55 +00:00
Jakob Stoklund Olesen
b2eeed7464 Revert r109652, and remove the offending assert in loadRegFromStackSlot instead.
We do sometimes load from a too small stack slot when dealing with x86 arguments
(varargs and smaller-than-32-bit args). It looks like we know what we are doing
in those cases, so I am going to remove the assert instead of artifically
enlarging stack slot sizes.

The assert in storeRegToStackSlot stays in. We don't want to write beyond the
bounds of a stack slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109764 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-29 17:42:27 +00:00
Jim Grosbach
542f642684 ARM mode version of r109693. Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109696 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 23:25:44 +00:00
Jim Grosbach
7946494ceb Remove incorrect substitution pattern for UXTB16. It wrongly assumed the input shift was actually a rotate. rdar://8240138
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 23:17:45 +00:00
Jim Grosbach
f0d7e36691 Remove dead prototype
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109691 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 23:16:12 +00:00
Jakob Stoklund Olesen
4c010ec851 Create a fixed stack object for varargs that is as large as any register.
The size of this object isn't used for anything - technically it is of variable
size.

This avoids a false positive from the assert in
X86InstrInfo::loadRegFromStackSlot, and fixes PR7735.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109652 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 20:55:38 +00:00
Dan Gohman
6d3b922670 Fix this code to avoid decrementing an iterator past the beginning
of a std::vector.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109597 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 17:15:36 +00:00
Dan Gohman
67d0498d53 Do GEP offset calculations with unsigned math rather than signed math
to avoid undefined behavior on overflow, noticed by John Regehr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109594 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 17:11:36 +00:00
Nate Begeman
51409214d7 Implement a vectorized algorithm for <16 x i8> << <16 x i8>
This is about 4x faster and smaller than the existing scalarization.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-28 00:21:48 +00:00
Nate Begeman
bdcb5afb77 ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller types coming in future patches.
For:

define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp {
entry:
  %shl = shl <4 x i32> %r, %a                     ; <<4 x i32>> [#uses=1]
  %tmp2 = bitcast <4 x i32> %shl to <2 x i64>     ; <<2 x i64>> [#uses=1]
  ret <2 x i64> %tmp2
}

We get:

_shl:                                   ## @shl
	pslld	$23, %xmm1
	paddd	LCPI0_0, %xmm1
	cvttps2dq	%xmm1, %xmm1
	pmulld	%xmm1, %xmm0
	ret

Instead of:

_shl:                                   ## @shl
	pshufd	$3, %xmm0, %xmm2
	movd	%xmm2, %eax
	pshufd	$3, %xmm1, %xmm2
	movd	%xmm2, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	pshufd	$1, %xmm0, %xmm3
	movd	%xmm3, %eax
	pshufd	$1, %xmm1, %xmm3
	movd	%xmm3, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm3
	punpckldq	%xmm2, %xmm3
	movd	%xmm0, %eax
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm2
	movhlps	%xmm0, %xmm0
	movd	%xmm0, %eax
	movhlps	%xmm1, %xmm1
	movd	%xmm1, %ecx
	shll	%cl, %eax
	movd	%eax, %xmm0
	punpckldq	%xmm0, %xmm2
	movdqa	%xmm2, %xmm0
	punpckldq	%xmm3, %xmm0
	ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 22:37:06 +00:00
Michael J. Spencer
dfd30187c6 Make MC use Windows COFF on Windows and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 06:46:15 +00:00
Jakob Stoklund Olesen
81c7b19f04 The isLoadFromStackSlot and isStoreToStackSlot have no way of reporting
subregister operands like this:

%reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8)

Make them return false when subreg operands are present. VirtRegRewriter is
making bad assumptions otherwise.

This fixes PR7713.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109489 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 04:17:01 +00:00
Jakob Stoklund Olesen
516cd4575e Add assertions that expose the PR7713 miscompilation: Accessing a stack slot
with a too-big register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109488 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-27 04:16:58 +00:00
Eli Friedman
a10213e934 And a bit more non-ASCII stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109458 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 22:28:18 +00:00
Anton Korobeynikov
4e084e93a7 Drop some non-ascii stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109456 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 22:23:07 +00:00
Evan Cheng
dee81010eb On x86, f32 / f64 nodes share the same registers as 128-bit vector values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 21:50:05 +00:00
Anton Korobeynikov
25a6ab0144 Add a note
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109448 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 21:48:35 +00:00
Bruno Cardoso Lopes
3c45734274 Temporary hack to let codegen assert or generate poor code in case
we are using AVX and no AVX version of the desired intruction is present,
this is better for incremental dev (without fallbacks it's easier to spot
what's missing). Not sure this is the best hack thought (we can also disable
all HasSSE* predicates by dinamically marking them 'false' if AVX is present)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 21:01:18 +00:00
Anton Korobeynikov
b5a0ef99f8 Currently EH lowering code expects typeinfo to be global only.
This assumption is not satisfied due to global mergeing.
Workaround the issue by temporary disablinge mergeing of const globals.
Also, ignore LLVM "special" globals. This fixes PR7716

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109423 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 18:45:39 +00:00
Evan Cheng
0944795b8c ARM fastisel isn't ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109421 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-26 18:32:55 +00:00
Douglas Gregor
037b5e4128 Remove extraneous semicolon
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109373 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-25 17:34:42 +00:00
Douglas Gregor
1984d98376 Unbreak CMake build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109372 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-25 17:10:14 +00:00
Anton Korobeynikov
cec36f4c11 Hook in GlobalMerge pass
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109359 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 21:52:08 +00:00
Evan Cheng
70017e44cd Add an ILP scheduler. This is a register pressure aware scheduler that's
appropriate for targets without detailed instruction iterineries.
The scheduler schedules for increased instruction level parallelism in
low register pressure situation; it schedules to reduce register pressure
when the register pressure becomes high.

On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2
by 16%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 00:39:05 +00:00
Bruno Cardoso Lopes
3c8e1bee63 Support x86 "eiz" and "riz" pseudo index registers in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-24 00:06:39 +00:00
Jim Grosbach
c2723a57f3 Use the appropriate register class for an i32 when adding ARM::LR to the
function live in set. This will give us tGPR for Thumb1 and GPR otherwise,
so the copy will be spillable. rdar://8224931

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109293 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 23:50:35 +00:00
Dale Johannesen
8086d5800d Revert 109076. It is wrong and was causing regressions. Add some
comments explaining why it was wrong.  8225024.

Fix the real problem in 8213383: the code that splits very large
blocks when no other place to put constants can be found was not
considering the case that the block contained a Thumb tablejump.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109282 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:50:23 +00:00
Evan Cheng
3144687df7 - Allow target to specify when is register pressure "too high". In most cases,
it's too late to start backing off aggressive latency scheduling when most
  of the registers are in use so the threshold should be a bit tighter.
- Correctly handle live out's and extract_subreg etc.
- Enable register pressure aware scheduling by default for hybrid scheduler.
  For ARM, this is almost always a win on # of instructions. It's runtime
  neutral for most of the tests. But for some kernels with high register
  pressure it can be a huge win. e.g. 464.h264ref reduced number of spills by
  54 and sped up by 20%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109279 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:39:59 +00:00
Bruno Cardoso Lopes
f64a7d49a0 Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109276 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 22:15:26 +00:00
Bruno Cardoso Lopes
f528d2b438 Add AVX version of CLMUL instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109248 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 18:41:12 +00:00
Gabor Greif
04577efaf2 fix constness warnings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109224 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 13:28:47 +00:00
Gabor Greif
9843688f97 do not (implicitly) dereference iterator many times, cache it instead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109222 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 10:23:01 +00:00
Bruno Cardoso Lopes
26a9142bd6 Declare CLMUL as a subtarget feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109207 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 01:22:45 +00:00
Bruno Cardoso Lopes
cdae7e8244 Add x86 CLMUL (Carry-less multiplication) cpu feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 01:17:51 +00:00
Bruno Cardoso Lopes
6b7e9168a4 Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 00:54:35 +00:00
Dale Johannesen
c76d23f2e2 The only supported calling convention for X86-64 uses
SSE, so we can't return floating point values if this
is disabled.  Detect this error for clang.

With SSE1 only, f64 is a problem; it can be done, but
neither llvm-gcc nor clang has ever generated correct
code for it.  Since nobody noticed this I think it's
OK to treat it as an error for now.

This also handles SSE-sized vectors of floating point.
8207686, 8204109.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109201 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 00:30:35 +00:00
Bruno Cardoso Lopes
06e6e101a0 Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109198 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-23 00:14:54 +00:00
Chris Lattner
2062875a7d eliminate the TargetInstrInfo::GetInstSizeInBytes hook.
ARM/PPC/MSP430-specific code (which are the only targets that
implement the hook) can directly reference their target-specific
instrinfo classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:27:00 +00:00
Bruno Cardoso Lopes
fb583a9842 Add remaining AVX instructions (most of them dealing with GR64 destinations. This complete the assembler support for the general AVX ISA. But we still miss instructions from FMA3 and CLMUL specific feature flags, which are now the next step
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109168 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:18:49 +00:00
Chris Lattner
134d8eec87 remove the JIT "NeedsExactSize" feature and supporting logic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109167 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:17:55 +00:00
Chris Lattner
1c55386dae switch a private implementation of GetFunctionSizeInBytes.
This is probably not the best way to implement "Force LR to 
be spilled if the Thumb function size is > 2048." do this, 
it should use the branch shortening infrastructure, but I'm
just preserving functionality here.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109165 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:14:33 +00:00
Chris Lattner
0123c1da35 X86MCInstLower now depends on AsmPrinter being around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109154 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:10:04 +00:00
Chris Lattner
456fdaf0ce instead of migrating it to the MC instruction encoder, just
rip out the implementation of X86InstrInfo::GetInstSizeInBytes.
The code being ripped out just implemented a copy and hacked up
version of the (old) instruction encoder, and is buggy and 
terrible in other ways.  Since "GetInstSizeInBytes" is really 
only there to support the JIT's "NeedsExactSize" hook (which
noone is using), just rip out the code.  I will rip out the
NeedsExactSize hook next.

This resolves rdar://7617809 - switch X86InstrInfo::GetInstSizeInBytes to use X86MCCodeEmitter



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109149 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 21:05:13 +00:00
Xerxes Ranby
99ccffe87e ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109125 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 17:28:34 +00:00
Gabor Greif
a399781289 undo 80 column trespassing I caused
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109092 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 10:37:47 +00:00
Chandler Carruth
30d35b8720 Mark an assert-only variable as used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-22 08:02:25 +00:00