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21944 Commits

Author SHA1 Message Date
David Blaikie
9cc178726f Fix use of uninitialized variable. 
Found by GCC's maybe-uninitialized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156780 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-14 21:48:19 +00:00
Brendon Cahoon
5262abb268 Revert 156634 upon request until code improvement changes are made. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156775 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-14 19:35:42 +00:00
Dan Gohman
a6063c6e29 Rename @llvm.debugger to @llvm.debugtrap. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156774 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-14 18:58:10 +00:00
Benjamin Kramer
51b49c5292 Hexagon: Initialize TBB to 0. 
Found by valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156744 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-13 15:13:22 +00:00
Sirish Pande
2b38c12643 Make sure new value jump is enabled for Hexagon V5 as well. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156700 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 05:54:15 +00:00
Sirish Pande
b33857040f Support for Hexagon feature, New Value Jump. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156698 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 05:10:30 +00:00
Akira Hatanaka
739572f069 Remove MipsEmitGPRestore.cpp. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156696 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:24:03 +00:00
Akira Hatanaka
8f16ab5bab Delete all functions that are no longer needed in MipsFunctionInfo, including 
the ones that get or set the frame index for the $gp save slot. 

Remove the piece of code in MipsFunctionInfo::getGlobalBaseReg() which returns
GP. This function should always return a virtual register.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156695 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:22:13 +00:00
Akira Hatanaka
93f0a823bf Stop reserving register $gp. Do not call isGPFI to check whether a frame object 
is the $gp save slot.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156694 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:21:18 +00:00
Akira Hatanaka
acf411bd4c Do not add the pass which restores $gp after every function call. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156693 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:19:51 +00:00
Akira Hatanaka
92d4aec573 Make the following changes in MipsISelLowering.cpp: 
- Stop creating stack frame objects needed for saving $gp.
- Insert a node that copies the global pointer register to register $gp
  before the call node. This will ensure $gp is valid at the entry of the
  called function.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156692 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:19:04 +00:00
Akira Hatanaka
30cec40241 Make the following changes in MipsFrameLowering.cpp: 
- Stop emitting instructions needed to initialize the global pointer register.
- Stop emitting .cprestore directive.
- Do not take into account the $gp save slot when computing stack size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156691 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 03:18:00 +00:00
Akira Hatanaka
4147e4d054 Make the following changes in MipsAsmPrinter.cpp: 
- Remove code which lowers pseudo SETGP01.
- Fix LowerSETGP01. The first two of the three instructions that are emitted to
  initialize the global pointer register now use register $2.
- Stop emitting .cpload directive.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156689 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 00:48:43 +00:00
Akira Hatanaka
27ba61df9f Insert instructions to the entry basic block which initializes the global 
pointer register. 


This is the first of the series of patches which clean up the way global pointer
register is used. The patches will make the following improvements:

- Make $gp an allocatable temporary register rather than reserving it.
- Use a virtual register as the global pointer register and let the register
  allocator decide which register to assign to it or whether spill/reloads are
  needed.
- Make sure $gp is valid at the entry of a called function, which is necessary
  for functions using lazy binding.
- Remove the need for emitting .cprestore and .cpload directives.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156671 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-12 00:17:17 +00:00
Akira Hatanaka
3011a33a63 Do not replace operands of pseudo instructions with register $zero. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156663 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 23:22:18 +00:00
Chad Rosier
226ddf5278 [fast-isel] Add support for selecting @llvm.trap(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156646 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 21:33:49 +00:00
Brendon Cahoon
927ede5a87 Updated instruction table due to addded intrinsics. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156644 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 21:10:16 +00:00
Sirish Pande
12a52525e8 Remove warnings from HexagonVLIWPacketizer. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156636 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 20:00:34 +00:00
Brendon Cahoon
6d532d8860 Hexagon constant extender support. 
Patch by Jyotsna Verma.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:56:59 +00:00
Chad Rosier
e1093e5503 Typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156633 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:43:29 +00:00
Chad Rosier
2b3b335f2d [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. Minor cleanup. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156632 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:40:25 +00:00
Sirish Pande
81e900d14c Hexagon V5 intrinsics support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156631 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 19:39:13 +00:00
Chad Rosier
2a2e9d54e9 [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-reg 
retval.  Hoists check before emitting the call to avoid unnecessary work.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156628 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 18:51:55 +00:00
Chad Rosier
2f6ae41f14 [fast-isel] Rather then assert (or segfault in a non-asserts build), fall back 
to selection DAG isel if we're unable to handle a non-double multi-reg retval.
rdar://11430407
PR12796


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156622 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 17:41:06 +00:00
Chad Rosier
f4bd21c256 The return type is an unsigned, not a bool. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156621 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 16:41:38 +00:00
Manman Ren
4949e98ccc Add space before an open parenthesis in control flow statements. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156620 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 15:36:46 +00:00
Preston Gurd
3c579c8343 Added X86 Atom latencies to X86InstrMMX.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 14:27:12 +00:00
Hans Wennborg
228756c744 Implement initial-exec TLS model for 32-bit PIC x86 
This fixes a TODO from 2007 :) Previously, LLVM would emit the wrong
code here (see the update to test/CodeGen/X86/tls-pie.ll).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156611 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 10:11:01 +00:00
Silviu Baranga
169e9ba2b2 Added the missing bit definition for the 4th bit of the STR (post reg) instruction. It is now set to 0. The patch also sets the unpredictable mask for SEL and SXTB-type instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156609 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 09:28:27 +00:00
Silviu Baranga
ca3cd419a5 Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 09:10:54 +00:00
Akira Hatanaka
2b7ab5eb49 Fix a misleading comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156603 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:45:15 +00:00
Manman Ren
247c5ab07c ARM: peephole optimization to remove cmp instruction 
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156599 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 01:30:47 +00:00
Dan Gohman
d4347e1af9 Define a new intrinsic, @llvm.debugger. It will be similar to __builtin_trap(), 
but it generates int3 on x86 instead of ud2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156593 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-11 00:19:32 +00:00
Preston Gurd
deaa3f3e52 Added X86 Atom latencies for instructions in X86InstrInfo.td. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156579 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:58:35 +00:00
Eric Christopher
05b7a50210 Add support for the 'X' inline asm operand modifier. 
Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156577 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 21:48:22 +00:00
Sirish Pande
0cfb5cfe97 Hexagon V5 Support - V5 td file. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156569 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 20:24:28 +00:00
Sirish Pande
7517bbc91a Hexagon V5 FP Support. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 20:20:25 +00:00
Manman Ren
fe65d98dad Revert: 156550 "ARM: peephole optimization to remove cmp instruction" 
This commit broke an external linux bot and gave a compile-time warning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156556 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 18:49:43 +00:00
Manman Ren
8ae4f062e4 ARM: peephole optimization to remove cmp instruction 
This patch will optimize the following cases:
  sub r1, r3 | sub r1, imm
  cmp r3, r1 or cmp r1, r3 | cmp r1, imm
  bge L1

TO
  subs r1, r3
  bge  L1 or ble L1

If the branch instruction can use flag from "sub", then we can replace
"sub" with "subs" and eliminate the "cmp" instruction.

rdar: 10734411


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156550 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 16:48:21 +00:00
Nadav Rotem
b88e8dd31d Fix merge-typo and cleanup 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156541 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 12:50:02 +00:00
Nadav Rotem
b210651654 AVX2: Add an additional broadcast idiom. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156540 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 12:39:13 +00:00
Nadav Rotem
5fc2187a02 Generate AVX/AVX2 shuffles even when there is a memory op somewhere else in the program. 
Starting r155461 we are able to select patterns for vbroadcast even when the load op is used by other users.

Fix PR11900.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156539 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-10 12:22:05 +00:00
Roman Divacky
d9b41b339d Mark .opd @progbits, thus avoiding a warning from asm. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156494 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 18:24:23 +00:00
Akira Hatanaka
2b409b65d4 Add another peephole pattern for conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156460 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 02:29:29 +00:00
Jakob Stoklund Olesen
cf661a040c Use ptr_rc_tailcall instead of GR32_TC. 
The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.

Patch by Yiannis Tsiouris!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 01:50:09 +00:00
Akira Hatanaka
56ec9f2c09 Make register FP allocatable if the compiled function does not have dynamic 
allocas.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156458 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 01:38:13 +00:00
Akira Hatanaka
a284acb8a7 Expand 64-bit shifts if target ABI is O32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156457 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 00:55:21 +00:00
Richard Trieu
220ee59b90 Remove unused variable to silence compiler warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156456 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-09 00:30:21 +00:00
Jakob Stoklund Olesen
f191b43103 Use a shared function for a common operation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156441 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 23:27:30 +00:00
Eric Christopher
22b291abd8 Remove excess semi-colons to quiet warnings. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156416 91177308-0d34-0410-b5e6-96231b3b80d8
 2012-05-08 20:45:04 +00:00