6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-18 14:31:27 +00:00
Code Issues Projects Releases Wiki Activity
73,097 Commits 39 Branches 0 Tags
Commit Graph

626 Commits

Author SHA1 Message Date
Chad Rosier
689edc8b28 Revision r128665 added an optimization to make use of NEON multiplier 
accumulator forwarding.  Specifically (from SVN log entry):

Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier
accumulator forwarding:
vadd d3, d0, d1
vmul d3, d3, d2
=>
vmul d3, d0, d2
vmla d3, d1, d2

Make sure it catches cases where operand 1 is add/fadd/sub/fsub, which was
intended in the original revision.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133127 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-16 01:21:54 +00:00
Bob Wilson
7a10ab7d6f A minor simplification: no functional change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133047 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 06:04:34 +00:00
Evan Cheng
bf188aeae7 PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff 
the bits being cleared by the AND are not demanded by the BFI.

The previous BFI dag combine rule was actually incorrect (or used to be
correct until BFI representation changed).

rdar://9609030


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133034 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-15 01:12:31 +00:00
Tanya Lattner
189531f317 Add an optimization that looks for a specific pair-wise add pattern and generates a vpaddl instruction instead of scalarizing the add. 
Includes a test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133027 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 23:48:48 +00:00
Bruno Cardoso Lopes
9a767330f5 Add one more argument to the prefetch intrinsic to indicate whether it's a data 
or instruction cache access. Update the targets to match it and also teach
autoupgrade.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132976 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-14 04:58:37 +00:00
Cameron Zwarich
a86686e643 Provide an ARMCCState subclass of CCState so that ARM clients will always set 
CallOrPrologue correctly and eliminate the existing setter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132856 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-10 20:59:24 +00:00
Cameron Zwarich
a2e979565b A CCState was being created without setting whether it is in the Call or Prologue state, 
causing an assertion failure downstream. This fixes <rdar://problem/9562908>.

This really seems like it should always be set at CCState creation time, so mistakes like
this can never happen. I'll take a look at doing that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132811 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-09 22:30:07 +00:00
Eric Christopher
471e422480 Add a parameter to CCState so that it can access the MachineFunction. 
No functional change.

Part of PR6965


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132763 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-08 23:55:35 +00:00
Eric Christopher
cf714d44b8 Make the Uv constraint a memory operand. This doesn't solve the 
addressing mode problem mentioned in r132559.

Backend part of rdar://9037836 and part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132561 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-03 17:24:37 +00:00
Eric Christopher
100c833416 Have LowerOperandForConstraint handle multiple character constraints. 
Part of rdar://9119939


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132510 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-06-02 23:16:42 +00:00
John McCall
5f8fd54f08 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).

Take 2, now with more basic competence.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132295 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:50:32 +00:00
John McCall
7eebab2a82 I didn't mean to commit these residues of a personal project. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132293 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:41:56 +00:00
John McCall
832a9d1a76 On Darwin ARM, set the UNWIND_RESUME libcall to _Unwind_SjLj_Resume. 
This is important for the correct lowering of unwind instructions
(which doesn't matter at all) and llvm.eh.resume calls (which does).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132291 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-29 19:39:04 +00:00
Bruno Cardoso Lopes
a0112d0c39 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs 
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132248 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-28 04:07:29 +00:00
Cameron Zwarich
de64aaf6c8 Fix the remaining atomic intrinsics to use the right register classes on Thumb2, 
and add some basic tests for them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132235 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 23:54:00 +00:00
Evan Cheng
4abce0c90b Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132211 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-27 20:11:27 +00:00
Renato Golin
1ec11fb8b5 RTABI chapter 4.3.4 specifies __eabi_mem* calls. Specifically, __eabi_memset accepts parameters (ptr, size, value) in a different order than GNU's memset (ptr, value, size), therefore the special lowering in AAPCS mode. Implementation by Evzen Muller. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131868 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-22 21:41:23 +00:00
Evan Cheng
0b65599015 Revert accidental commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 17:38:48 +00:00
Evan Cheng
2e6496026f Revert r131664 and fix it in instcombine instead. rdar://9467055 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-20 00:54:37 +00:00
Mon P Wang
28e2b1d29a Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131630 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-19 04:15:07 +00:00
Tanya Lattner
db28247522 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131582 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 21:44:54 +00:00
Evan Cheng
b936e3006f Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131555 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 18:59:17 +00:00
Evan Cheng
d48fda46f5 Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131553 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 18:47:27 +00:00
Tanya Lattner
2a8eb722c7 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131529 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 06:42:21 +00:00
Cameron Zwarich
141ec63962 Fix typo. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131519 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 02:29:50 +00:00
Cameron Zwarich
7d336c0c68 Fix more of PR8825 by correctly using rGPR registers when lowering atomic 
compare-and-swap intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131518 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-18 02:20:07 +00:00
Bill Wendling
61512ba251 Give the 'eh.sjlj.dispatchsetup' intrinsic call the value coming from the setjmp 
intrinsic call. This prevents it from being reordered so that it appears
*before* the setjmp intrinsic (thus making it completely useless).
<rdar://problem/9409683>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131174 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-11 01:11:55 +00:00
Eli Friedman
fc5d305597 Make the logic for determining function alignment more explicit. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131012 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-06 20:34:06 +00:00
Bob Wilson
e1a56ae747 Temporarily disable use of divmod compiler-rt functions for iOS. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130766 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 17:33:22 +00:00
Dan Gohman
cca82149ad Add an unfolded offset field to LSR's Formula record. This is used to 
model constants which can be added to base registers via add-immediate
instructions which don't require an additional register to materialize
the immediate.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130743 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-05-03 00:46:49 +00:00
Eric Christopher
5ac179ccd2 80-col. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-29 23:12:01 +00:00
Jim Grosbach
f7da8821b4 ARM and Thumb2 support for atomic MIN/MAX/UMIN/UMAX loads. 
rdar://9326019


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130234 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-26 19:44:18 +00:00
Andrew Trick
1c3af779fc Thumb2 and ARM add/subtract with carry fixes. 
Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>.
t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the
assembly printer correctly prints the 's' suffix.

Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags.

Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS.
Fixes ARM SBC lowering to check for live carry (potential bug).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130048 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-23 03:55:32 +00:00
Evan Cheng
c8578948c9 Remove -use-divmod-libcall. Let targets opt in when they are available. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 22:20:12 +00:00
Stuart Hastings
e341e8ce1a Excise unintended hunk in 129858. <rdar://problem/7662569> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129862 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 18:09:26 +00:00
Stuart Hastings
c73158730d ARM byval support. Will be enabled by another patch to the FE. <rdar://problem/7662569> 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129858 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-20 16:47:52 +00:00
Eric Christopher
2cc4013853 Remove some duplicate op action entries and reorganize. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129781 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-19 18:49:19 +00:00
Chris Lattner
7a2bdde0a0 Fix a ton of comment typos found by codespell. Patch by 
Luis Felipe Strano Moraes!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 05:18:47 +00:00
Evan Cheng
9eec66e604 Fix another fcopysign lowering bug. If src is f64 and destination is f32, don't 
forget to right shift the source by 32 first. rdar://9287902


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-15 01:31:00 +00:00
Cameron Zwarich
5af60ce2a8 Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-13 21:01:19 +00:00
Cameron Zwarich
d0aacbcc2e Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARM 
stores of arguments in the same cache line. This fixes the second half of
<rdar://problem/8674845>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-12 02:24:17 +00:00
Evan Cheng
4da0c7c0c9 Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap is lowered into a call to the specified trap function at sdisel time. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-08 21:37:21 +00:00
Evan Cheng
274d8d4eba Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129107 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 20:31:12 +00:00
Tanya Lattner
0433b21c98 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129074 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 15:24:20 +00:00
Evan Cheng
2c69f8eec6 Change -arm-divmod-libcall to a target neutral option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129045 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-07 00:58:44 +00:00
Owen Anderson
b48c791515 Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128965 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:55:28 +00:00
Owen Anderson
493cba1b32 Revert r128946 while I figure out why it broke the buildbots. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128951 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 23:03:06 +00:00
Owen Anderson
76634dfabb Give RSBS and RSCS the pseudo treatment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128946 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 22:42:54 +00:00
Owen Anderson
7670601313 Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128940 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 21:48:57 +00:00
Bill Wendling
f05b1dcf87 Revamp the SjLj "dispatch setup" intrinsic. 
It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128873 91177308-0d34-0410-b5e6-96231b3b80d8
 2011-04-05 01:37:43 +00:00