Commit Graph

93 Commits

Author SHA1 Message Date
c0b9dc5be7 Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11340 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-12 02:27:10 +00:00
1cbe4d0ad0 Do not use MachineOperand::isVirtualRegister either!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11283 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-10 21:12:22 +00:00
3d878d80d6 Eliminate users of MachineOperand::isPhysicalRegister
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11278 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-10 20:41:10 +00:00
ecea5635f8 Another nice speedup for the register allocator. This time, we replace
the Virt2PhysRegMap std::map with an std::vector.  This speeds up the
register allocator another (almost) 40%, from .72->.45s in a release build
of LLC on 253.perlbmk.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11219 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-09 02:12:04 +00:00
64667b6418 Change the PhysRegsUsed map into a dense array. Seeing that this is a mapping
from physical registers, and they are always dense, it makes sense to not have
a ton of RBtree overhead.  This change speeds up regalloclocal about ~30% on
253.perlbmk, from .35s -> .27s in the JIT (in LLC, it goes from .74 -> .55).

Now live variable analysis is the slowest codegen pass.  Of course it doesn't
help that we have to run it twice, because regalloclocal doesn't update it,
but even if it did it would be the slowest pass (now it's just the 2x slowest
pass :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11215 91177308-0d34-0410-b5e6-96231b3b80d8
2004-02-09 01:26:13 +00:00
ef09c63e7b Finegrainify namespacification, use new MRegisterInfo::isVirtualRegister
method


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11037 91177308-0d34-0410-b5e6-96231b3b80d8
2004-01-31 21:27:19 +00:00
19b6486d38 Correctly compute live variable information for physical registers
when an implicitely defined register is later used by an alias. For example:

         call foo
         %reg1024 = mov %AL

The call implicitely defines EAX but only AL is used. Before this fix
no information was available on AL. Now EAX and all its aliases except
AL get defined and die at the call instruction whereas AL lives to be
killed by the assignment.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10813 91177308-0d34-0410-b5e6-96231b3b80d8
2004-01-13 06:24:30 +00:00
4c080863de Remove TwoAddressInstruction from the public headers and add an ID
instead, since this pass doesn't expose any state to its users.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10520 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-18 22:40:24 +00:00
9af9dbde7d Modify local register allocator to use the two-address instruction pass.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10513 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-18 13:08:52 +00:00
4d7af65903 Change interface of MachineOperand as follows:
a) remove opIsUse(), opIsDefOnly(), opIsDefAndUse()
    b) add isUse(), isDef()
    c) rename opHiBits32() to isHiBits32(),
              opLoBits32() to isLoBits32(),
              opHiBits64() to isHiBits64(),
              opLoBits64() to isLoBits64().

This results to much more readable code, for example compare
"op.opIsDef() || op.opIsDefAndUse()" to "op.isDef()" a pattern used
very often in the code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10461 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-14 13:24:17 +00:00
efe995a406 Remove unecessary if statements when looping on ImplicitDefs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10444 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-13 01:20:58 +00:00
a327e7fea9 Make assertion stricter. Since the source operands are allocated at
this point, the second operand must be a physical register (it cannot
be a virtual one).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10292 91177308-0d34-0410-b5e6-96231b3b80d8
2003-12-05 11:31:39 +00:00
d0fde30ce8 Put all LLVM code into the llvm namespace, as per bug 109.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9903 91177308-0d34-0410-b5e6-96231b3b80d8
2003-11-11 22:41:34 +00:00
3e43026095 standardize command line option names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9496 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-24 20:05:58 +00:00
b576c94c15 Added LLVM project notice to the top of every C++ source file.
Header files will be on the way.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9298 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-20 19:43:21 +00:00
73ff5120eb Change MRegisterDesc::AliasSet, TargetInstrDescriptor::ImplicitDefs
and TargetInstrDescriptor::ImplicitUses to always point to a null
terminated array and never be null. So there is no need to check for
pointer validity when iterating over those sets. Code that looked
like:

if (const unsigned* AS = TID.ImplicitDefs) {
  for (int i = 0; AS[i]; ++i) {
    // use AS[i]
  }
}

was changed to:

for (const unsigned* AS = TID.ImplicitDefs; *AS; ++AS) {
  // use *AS
}


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8960 91177308-0d34-0410-b5e6-96231b3b80d8
2003-10-08 05:20:08 +00:00
41822c790f Fix bug: Jello/2003-08-23-RegisterAllocatePhysReg.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8095 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-23 23:49:42 +00:00
128c2aa493 Fix bug: Jello/2003-08-15-AllocaAssertion.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7916 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-17 18:01:15 +00:00
53b99a0fe7 Fix typo in comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7906 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-15 21:19:25 +00:00
19df3876e6 Factory methods for FunctionPasses now return type FunctionPass *.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7823 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-13 18:18:15 +00:00
8c8194500d Fix bugs handling ESP in alloca references
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7591 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-05 04:13:58 +00:00
d9ac6a7d3b Revert previous change, and be really anal about what physical registers can do.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7588 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-05 00:49:09 +00:00
27615d7f21 Don't bother calculating info unless its needed. May reduce number of stack slots created.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7584 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 23:42:37 +00:00
b8822ad224 * Fix spelling of 'necessary'
* Add a lot more DEBUG output, which is better structured than before
* Fix bug: Jello/2003-08-04-PhysRegLiveFailure.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7583 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-04 23:36:39 +00:00
4cc662b0ef Set debug types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7533 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 21:47:31 +00:00
d3fd79f699 Wrap at 80 columns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7503 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-03 13:49:03 +00:00
a11136b16c Move DEBUG to Debug.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7497 91177308-0d34-0410-b5e6-96231b3b80d8
2003-08-01 22:21:34 +00:00
5f2180c533 (1) Added special register class containing (for now) %fsr.
Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

(3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly()
    and related functions and flags.  Fixed several bugs where only
    "isDef" was being checked, not "isDefAndUse".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-27 00:05:23 +00:00
d5725631c5 Fix tab infestation!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6109 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-12 03:54:14 +00:00
15b55e20cc Debug output should go to cerr, not cout, because that's where bytecode goes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6002 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-04 22:51:30 +00:00
0416d2a70a Fix problems with empty basic blocks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5326 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-16 18:06:43 +00:00
3501feab81 Rename MachineInstrInfo -> TargetInstrInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5272 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-14 22:00:31 +00:00
91a452b382 * Convert to use LiveVariable analysis
* Convert to use PHIElimination pass
* Don't spill values which have just been reloaded (big win reducing spills)
* Add experimental support for eliminating spills before TwoAddress
  instructions.  It currently is broken so it is #ifdef'd out.
* Use new "is terminator" flag on instructions instead of looking for
  branches and returns explicitly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5219 91177308-0d34-0410-b5e6-96231b3b80d8
2003-01-13 00:25:40 +00:00
eb24db9727 Rename FunctionFrameInfo to MachineFrameInfo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5200 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 21:08:26 +00:00
580f9be7ff * Convert to be a MachineFunctionPass instance
* Use new FunctionFrameInfo object to manage stack slots instead of doing
  it directly
* Adjust to new MRegisterInfo API
* Don't take a TM as a ctor argument
* Don't keep track of which callee saved registers are modified
* Don't emit prolog/epilog code or spill/restore code for callee saved regs
* Use new allocation_order_begin/end iterators to simplify dramatically the
  logic for picking registers to allocate
* Machine PHI nodes can no longer contain constant arguments


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5195 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-28 20:40:43 +00:00
ff863ba610 Adjust to simpler spill interface
Only spill and reload caller saved registers that are actually modified.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5145 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-25 05:05:46 +00:00
0eb172cc4a Substantial fixes to live range handling, fixing several problems, getting
strtol to not miscompile, and fixing bug: 2002-12-23-LocalRAProblem.llx


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5132 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-24 00:04:55 +00:00
82bee0f2c8 * Fix several register aliasing bugs
* Add a new option to eliminate spilling of registers that are only used
  within a basic block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5106 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-18 08:14:26 +00:00
e7d361d15a Use new reginfo interface
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5099 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-17 04:19:40 +00:00
86c69a6cbe Add prolog/epilog spills/reloads to counters
Move X86 specific alignment gunk to X86 files


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5096 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-17 03:16:10 +00:00
ae64043737 Fix many bugs, regallocator now saves callee-save registers instead of target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5093 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-17 02:50:10 +00:00
c21be922bf * Fix a gross X86 hack that was intended to avoid allocating SP and BP
* Implement register alias set support


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5082 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-16 17:44:42 +00:00
b74e83c898 Initial checkin of "local" register allocator. Bugs are still present.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5078 91177308-0d34-0410-b5e6-96231b3b80d8
2002-12-16 16:15:28 +00:00